This is FLOGB, FCVTZS, FCVTZU.
Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/translate-sve.c | 37 ++++++++++++++++++++++++++++++++--
target/arm/tcg/sve.decode | 16 +++++++++++++++
2 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 841f625c25..315ebe82f9 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4654,6 +4654,37 @@ TRANS_FEAT(FCVTZS_dd_m, aa64_sme_or_sve,
gen_gvec_fpst_arg_zpz,
TRANS_FEAT(FCVTZU_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64)
+TRANS_FEAT(FCVTZS_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_hh, a, 1, FPST_A64_F16)
+TRANS_FEAT(FCVTZU_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_hh, a, 1, FPST_A64_F16)
+TRANS_FEAT(FCVTZS_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_hs, a, 1, FPST_A64_F16)
+TRANS_FEAT(FCVTZU_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_hs, a, 1, FPST_A64_F16)
+TRANS_FEAT(FCVTZS_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_hd, a, 1, FPST_A64_F16)
+TRANS_FEAT(FCVTZU_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_hd, a, 1, FPST_A64_F16)
+
+TRANS_FEAT(FCVTZS_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_ss, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZU_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_ss, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZS_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_sd, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZU_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_sd, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZS_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_ds, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZU_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_ds, a, 1, FPST_A64)
+
+TRANS_FEAT(FCVTZS_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzs_dd, a, 1, FPST_A64)
+TRANS_FEAT(FCVTZU_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_fcvtzu_dd, a, 1, FPST_A64)
+
static gen_helper_gvec_3_ptr * const frint_fns[] = {
NULL,
gen_helper_sve_frint_h,
@@ -8134,8 +8165,10 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,
gen_helper_flogb_s, gen_helper_flogb_d
};
-TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
+TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
+ flogb_fns[a->esz], a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
+TRANS_FEAT(FLOGB_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ flogb_fns[a->esz], a, 1, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
index 673cbaae57..2795c2ec7f 100644
--- a/target/arm/tcg/sve.decode
+++ b/target/arm/tcg/sve.decode
@@ -1242,6 +1242,21 @@ FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... .....
@rd_pg_rn_e0
FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_hh_z 01100100 01 011 11 0 110 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_hh_z 01100100 01 011 11 0 111 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_hs_z 01100100 01 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_hs_z 01100100 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_hd_z 01100100 01 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_hd_z 01100100 01 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_ss_z 01100100 10 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_ss_z 01100100 10 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_sd_z 01100100 11 011 11 1 100 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_sd_z 01100100 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_ds_z 01100100 11 011 11 0 100 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_ds_z 01100100 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
+FCVTZS_dd_z 01100100 11 011 11 1 110 ... ..... ..... @rd_pg_rn_e0
+FCVTZU_dd_z 01100100 11 011 11 1 111 ... ..... ..... @rd_pg_rn_e0
+
# SVE floating-point round to integral value
FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
@@ -1950,6 +1965,7 @@ FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... .....
@rd_pg_rn_e0
### SVE2 floating-point convert to integer
FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
+FLOGB_z 01100100 00 011 1101 esz:2 pg:3 rn:5 rd:5 &rpr_esz
### SVE2 floating-point multiply-add long (vectors)
FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
--
2.43.0
