Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/tcg/sve.decode | 16 ++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 9e0945252d..936396103f 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4784,6 +4784,40 @@ TRANS_FEAT(UCVTF_sd_m, aa64_sme_or_sve,
gen_gvec_fpst_arg_zpz,
TRANS_FEAT(UCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_ucvt_dd, a, 0, FPST_A64)
+TRANS_FEAT(SCVTF_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_hh, a, 1, FPST_A64_F16)
+TRANS_FEAT(SCVTF_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_sh, a, 1, FPST_A64_F16)
+TRANS_FEAT(SCVTF_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_dh, a, 1, FPST_A64_F16)
+
+TRANS_FEAT(SCVTF_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_ss, a, 1, FPST_A64)
+TRANS_FEAT(SCVTF_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_ds, a, 1, FPST_A64)
+
+TRANS_FEAT(SCVTF_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_sd, a, 1, FPST_A64)
+TRANS_FEAT(SCVTF_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_scvt_dd, a, 1, FPST_A64)
+
+TRANS_FEAT(UCVTF_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_hh, a, 1, FPST_A64_F16)
+TRANS_FEAT(UCVTF_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_sh, a, 1, FPST_A64_F16)
+TRANS_FEAT(UCVTF_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_dh, a, 1, FPST_A64_F16)
+
+TRANS_FEAT(UCVTF_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_ss, a, 1, FPST_A64)
+TRANS_FEAT(UCVTF_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_ds, a, 1, FPST_A64)
+TRANS_FEAT(UCVTF_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_sd, a, 1, FPST_A64)
+
+TRANS_FEAT(UCVTF_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
+ gen_helper_sve_ucvt_dd, a, 1, FPST_A64)
+
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
index c39d80360f..7460eee4a9 100644
--- a/target/arm/tcg/sve.decode
+++ b/target/arm/tcg/sve.decode
@@ -1283,6 +1283,22 @@ UCVTF_sd_m 01100101 11 010 00 1 101 ... ..... .....
@rd_pg_rn_e0
UCVTF_ds_m 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
UCVTF_dd_m 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
+SCVTF_hh_z 01100100 01 011 10 0 110 ... ..... ..... @rd_pg_rn_e0
+SCVTF_sh_z 01100100 01 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
+SCVTF_ss_z 01100100 10 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
+SCVTF_sd_z 01100100 11 011 10 0 100 ... ..... ..... @rd_pg_rn_e0
+SCVTF_dh_z 01100100 01 011 10 1 110 ... ..... ..... @rd_pg_rn_e0
+SCVTF_ds_z 01100100 11 011 10 1 100 ... ..... ..... @rd_pg_rn_e0
+SCVTF_dd_z 01100100 11 011 10 1 110 ... ..... ..... @rd_pg_rn_e0
+
+UCVTF_hh_z 01100100 01 011 10 0 111 ... ..... ..... @rd_pg_rn_e0
+UCVTF_sh_z 01100100 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
+UCVTF_ss_z 01100100 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
+UCVTF_sd_z 01100100 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
+UCVTF_dh_z 01100100 01 011 10 1 111 ... ..... ..... @rd_pg_rn_e0
+UCVTF_ds_z 01100100 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
+UCVTF_dd_z 01100100 11 011 10 1 111 ... ..... ..... @rd_pg_rn_e0
+
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register
--
2.43.0
