The translator has supported mnret since commit 3157a553ec6b9a
("target/riscv: Add Smrnmi mnret instruction"), but the
disassembler still renders it as illegal. Add it unguarded,
since the encoding does not overlap any other extension.Signed-off-by: imaginos <[email protected]> --- disas/riscv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index d416a4d6b3..065985992b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -985,6 +985,7 @@ typedef enum { rv_op_ssamoswap_d = 953, rv_op_c_sspush = 954, rv_op_c_sspopchk = 955, + rv_op_mnret = 956, } rv_op; /* register names */ @@ -2255,6 +2256,7 @@ const rv_opcode_data rvi_opcode_data[] = { rv_op_sspush, 0 }, { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, rv_op_sspopchk, 0 }, + { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, }; /* CSR names */ @@ -4050,6 +4052,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 64: op = rv_op_mret; break; } break; + case 1792: + switch ((inst >> 15) & 0b1111111111) { + case 64: op = rv_op_mnret; break; + } + break; case 1952: switch ((inst >> 15) & 0b1111111111) { case 576: op = rv_op_dret; break; -- 2.43.0
