OpenBSD/powernv programs PTCR for LPID 0 with a partition table size exponent one smaller than QEMU's existing ISA v3.0 interpretation. Try QEMU's existing PATS interpretation first, then fall back to the OpenBSD LPID 0 form; nonzero LPIDs keep the old behaviour.
The PSI model now exposes POWER9 IRQ level and pending status registers, and keeps both updated while delivering through the existing XIVE LSI source. This lets guests that select the POWER9 PSI LSI IRQ method continue to receive LPC interrupts. The blast radius is probably minimal: the partition table fallback is limited to bare metal LPID 0 after the original lookup fails, while the PSI change only touches POWER9 PSI state and reuses the existing delivery path. Signed-off-by: Kirill A. Korinsky <[email protected]> --- hw/ppc/pnv_psi.c | 17 ++++++++--------- target/ppc/mmu-book3s-v3.c | 33 ++++++++++++++++++++++++++++----- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index e8701c6100..941540df2d 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -688,6 +688,8 @@ static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) case PSIHB9_ESB_CI_BASE: case PSIHB9_ESB_NOTIF_ADDR: case PSIHB9_IVT_OFFSET: + case PSIHB9_IRQ_LEVEL: + case PSIHB9_IRQ_STAT: val = psi->regs[reg]; break; default: @@ -817,18 +819,15 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = { static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) { PnvPsi *psi = opaque; - uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; + uint64_t irq_bit = PPC_BIT(irq); - if (irq_method & PSIHB9_IRQ_METHOD) { - qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); - return; - } - - /* Update LSI levels */ + /* Update LSI levels and pending status */ if (state) { - psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= irq_bit; + psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] |= irq_bit; } else { - psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~irq_bit; + psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] &= ~irq_bit; } qemu_set_irq(psi->qirqs[irq], state); diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c index 3865556310..4babe4c536 100644 --- a/target/ppc/mmu-book3s-v3.c +++ b/target/ppc/mmu-book3s-v3.c @@ -23,19 +23,21 @@ #include "mmu-hash64.h" #include "mmu-book3s-v3.h" -bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) +static bool ppc64_v3_get_pate_from_size(PowerPCCPU *cpu, target_ulong lpid, + ppc_v3_pate_t *entry, + uint64_t table_size) { uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; - uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; + uint64_t entries; /* Check if partition table is properly aligned */ - if (patb & MAKE_64BIT_MASK(0, pats + 12)) { + if (patb & (table_size - 1)) { return false; } /* Calculate number of entries */ - pats = 1ull << (pats + 12 - 4); - if (pats <= lpid) { + entries = table_size / sizeof(*entry); + if (entries <= lpid) { return false; } @@ -45,3 +47,24 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); return true; } + +bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) +{ + uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; + + /* + * Keep the existing ISA v3.0 PATS interpretation first. OpenBSD/powernv + * uses the PATSIZE value it writes to PTCR as one exponent smaller, and it + * only needs that interpretation for the bare metal LPID 0 table. + */ + if (ppc64_v3_get_pate_from_size(cpu, lpid, entry, 1ull << (pats + 12))) { + return true; + } + + if (lpid == 0) { + return ppc64_v3_get_pate_from_size(cpu, lpid, entry, + 1ull << (pats + 11)); + } + + return false; +} -- 2.54.0
