On Tue, 2 Jun 2026 15:41:25 +0800 Chen Pei <[email protected]> wrote:
> On RISC-V QEMU virt platform with CXL enabled, the probe ordering > of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not > guaranteed. If cxl_acpi probes before acpi_pci_root has attached > the CXL host bridges, the CXL port topology will be incomplete > because to_cxl_host_bridge() silently skips devices whose PCI root > is not yet ready. > > Add a _DEP object to the ACPI0017 device in the DSDT, declaring > its dependency on the ACPI0016 CXL host bridge devices. This tells > the OS to defer ACPI0017 enumeration until all ACPI0016 devices > have been attached by acpi_pci_root. > > This requires a corresponding kernel change to call > acpi_dev_clear_dependencies() in acpi_pci_root_add(). > > Signed-off-by: Chen Pei <[email protected]> It may be a good idea to add a bios tables test as well. We only have the x86 q35 one today because I argued at the time the ARM64 one would be just duplication. Now we have this new _DEP stuff we should probably add something to cover it. Please also include an iasl -d dump of the relevant additions to DSDT in the patch description. Much easier to review than the code that generates it! In general looks fine to me and great that you are clearing this up. Seems it's luck that x86 and ARM64 worked without this (or strictly speaking other things enforcing the ordering). Ultimately we probably want to add this to those two architectures a well. One small thing inline. Thanks, Jonathan > --- > hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index 309d64b322..a5bafd1dcf 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -510,6 +510,38 @@ static void build_dsdt(GArray *table_data, > if (s->cxl_devices_state.is_enabled) { > Aml *cxl_dev = aml_device("CXLM"); > aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); > + > + /* > + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS > + * defers ACPI0017 enumeration until acpi_pci_root has attached > + * the CXL host bridges. Without this, cxl_acpi may probe before > + * to_cxl_host_bridge() can resolve the PCI root and the CXL > + * port topology comes up empty. > + */ > + if (s->bus) { > + PCIBus *bus; > + uint32_t num_cxl_hbs = 0; > + > + QLIST_FOREACH(bus, &s->bus->child, sibling) { > + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { > + num_cxl_hbs++; I think you only care if there is at least one. Instead of counting, just set a bool and break out early if you find one. > + } > + } > + > + if (num_cxl_hbs > 0) { > + Aml *dep_pkg = aml_package(num_cxl_hbs); > + > + QLIST_FOREACH(bus, &s->bus->child, sibling) { > + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { > + aml_append(dep_pkg, > + aml_name("\\_SB.PC%.02X", > + pci_bus_num(bus))); > + } > + } > + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); > + } > + } > + > Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED); > aml_append(method, aml_return(aml_int(0x0B))); > aml_append(cxl_dev, method);
