On Tue, 9 Jun 2026 at 08:49, Eric Auger <[email protected]> wrote: > > Hi Nathan, Peter, > > On 6/8/26 7:48 PM, Nathan Chen wrote: > > Hi, > > > > This is a follow-up to the series [0] that introduces support for > > resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE, > > and OAS feature properties based on host IOMMU capabilities. This is > > dependent on the series [1] for changing these property types to accept > > 'auto' values. > > > > Accelerated SMMUv3 Address Translation Services support is derived from > > IDR0, Range Invalidation support is derived from IDR3, Substream ID > > size is derived from IDR1, and output address space is derived from > > IDR5. > > > > The default values are set to 'auto' for all properties. If accel=off > > and the values are set to 'auto' or are omitted and resolve to 'auto', > > the default property values defined in smmuv3_init_id_regs() for OAS > > and RIL will remain unchanged, while SSIDSIZE and ATS values will > > remain initialized at 0. > > > > A complete branch can be found here: > > https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v6 > > > > Please take a look and let me know your feedback. > > The series looks good to me and I tested it with Grace-Hopper GPU > passthrough > with explicit option settings and auto settings. It collected R-bs for > all the patches. Feel free to collect my T-b: > > Tested-by: Eric Auger <[email protected]> > > Peter, please could you consider pulling it if it suits you.
Thanks for taking on the testing and review for this -- I've applied it to target-arm.next. -- PMM
