From: Jay Chang <[email protected]> Align SPEC: Bare mode contexts are not cached, so they require direct memory deallocation via g_free instead of hash table cleanup.
Signed-off-by: Jay Chang <[email protected]> Reviewed-by: Frank Chang <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Nutty Liu <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- hw/riscv/riscv-iommu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 5b28b1ad63..a500cb8440 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1390,7 +1390,16 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s, static void riscv_iommu_ctx_put(RISCVIOMMUState *s, void *ref) { - if (ref) { + unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE); + + if (!ref) { + return; + } + + /* ref is pointing to ctx in Bare mode. Bare mode ctx is not cached */ + if (mode == RISCV_IOMMU_DDTP_MODE_BARE) { + g_free(ref); + } else { g_hash_table_unref((GHashTable *)ref); } } -- 2.54.0
