From: Frank Chang <[email protected]>
Smrnmi CPU fields introduced by commit: #5db557f should be reset when
the CPU resets, so move these fields above the CPU reset line.
Fixes: 5db557f82bff ("target/riscv: Add Smrnmi CSRs")
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
---
target/riscv/cpu.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index febd905389..eec5acea5f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -491,6 +491,15 @@ struct CPUArchState {
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
uint64_t henvcfg;
+
+ /* RNMI */
+ uint64_t mnscratch;
+ uint64_t mnepc;
+ uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */
+ uint64_t mnstatus;
+ uint64_t rnmip;
+ uint64_t rnmi_irqvec;
+ uint64_t rnmi_excpvec;
#endif
/* Fields from here on are preserved across CPU reset. */
@@ -509,15 +518,6 @@ struct CPUArchState {
uint64_t kvm_timer_state;
uint64_t kvm_timer_frequency;
#endif /* CONFIG_KVM */
-
- /* RNMI */
- uint64_t mnscratch;
- uint64_t mnepc;
- uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */
- uint64_t mnstatus;
- uint64_t rnmip;
- uint64_t rnmi_irqvec;
- uint64_t rnmi_excpvec;
};
/*
--
2.54.0
