From: Anton Johansson <[email protected]> Widen to 64 bits, and use hwaddr as argument to get_physical_address().
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 3 +-- target/riscv/machine.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2cc1b68f34..50f9ce1f86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -238,7 +238,7 @@ struct CPUArchState { uint64_t badaddr; uint64_t bins; - target_ulong guest_phys_fault_addr; + uint64_t guest_phys_fault_addr; target_ulong priv_ver; target_ulong vext_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f81354c90d..a25727b0da 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1236,7 +1236,7 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr) */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *ret_prot, vaddr addr, - target_ulong *fault_pte_addr, + hwaddr *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, bool is_debug, bool is_probe) @@ -1876,7 +1876,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, ret = get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_type, mmu_idx, true, true, false, probe); - /* * A G-stage exception may be triggered during two state lookup. * And the env->guest_phys_fault_addr has already been set in diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b7790c14d0..a4d337c27a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -458,7 +458,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINT64(env.badaddr, RISCVCPU), - VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), + VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), -- 2.54.0
