On 16.06.2026 23:12, Daniel Henrique Barboza wrote: ...
Daniel Henrique Barboza (24): target/riscv/tcg: disable svpbmt if satp_mode < sv39 target/riscv/csr.c: do not allow mstatus MPV/GVA writes target/riscv/csr.c: fix mstatus.UXL reserved value disas/riscv.c: add 'cbo' insns to disassembler target/riscv/insn_trans/trans_rvzicbo.c.inc: save opcode before helpers target/riscv/cpu_helper.c: fault with reserved PTE.PBMT val target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault target/riscv/cpu_helper.c: add PMA access fault target/riscv/tcg: disable svnapot if satp_mode < sv39 disas/riscv.c: fix inst_length() hw/riscv/virt.c: fix 'iommu-map' FDT entry hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc hw/riscv: add fdt-common helper hw/riscv/numa: make numa_enabled() public hw/riscv: add create_fdt_socket_memory() helper hw/riscv/sifive_u.c: add intc_phandles array hw/riscv/spike.c: add intc_phandles array hw/riscv: add create_fdt_clint() helper hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs hw/riscv: add fdt_create_cpu_socket_subnode() helper hw/riscv: add create_fdt_socket_cpus() hw/riscv/spike.c: use create_fdt_socket_cpus() hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal() hw/riscv: add create_fdt_socket_cpu_sifive()
From my patches I believe you can pick all the patches that have a "Resolves" tag. All of them are fixing stuff introduced several releases ago that people on Gitlab found. Should apply without too much hassle in stable 10.0.x and above.
This makes sense. You used Fixes at least once, instead of resolves, in "target/riscv/csr.c: fix mstatus.UXL reserved value", but that's Ok. I'm NOT picking up target/riscv/tcg: disable svnapot if satp_mode < sv39 target/riscv/tcg: disable svpbmt if satp_mode < sv39 to 10.0.x because it doesn't have max_satp_mode field in RISCVCPUConfig (it misses commit 357ce8171a9c75 "target/riscv: cpu: store max SATP mode as a single integer"). Thank you! /mjt
