On Tue, 9 Jun 2026 16:28:32 +0530 Shrihari E S <[email protected]> wrote:
> Add Unordered IO (UIO) dependent property SVC to CXL ports > (Root, Upstream and Downstream). > > The following properties are added to CXL ports: > - x-uio-svc: Enable UIO traffic via SVC3 (mandatory path) > - x-uio-svc-opt: Enable UIO traffic via SVC4 (optional path) > > Note: 256B flit mode property was already added in CXL ports, so reused it. > > Signed-off-by: Shrihari E S <[email protected]> > Signed-off-by: Dongjoo Seo <[email protected]> > --- > hw/pci-bridge/cxl_downstream.c | 2 ++ > hw/pci-bridge/cxl_root_port.c | 1 + > hw/pci-bridge/cxl_upstream.c | 2 ++ > include/hw/pci-bridge/cxl_upstream_port.h | 1 + > 4 files changed, 6 insertions(+) > > diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c > index 7c7a1d1221..6f6f332c07 100644 > --- a/hw/pci-bridge/cxl_downstream.c > +++ b/hw/pci-bridge/cxl_downstream.c > @@ -260,6 +260,8 @@ static const Property cxl_dsp_props[] = { > DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > width, PCIE_LINK_WIDTH_16), > DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), > + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), > + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, false), > }; > > static void cxl_dsp_class_init(ObjectClass *oc, const void *data) > diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c > index e82685d1ab..83fb5968b8 100644 > --- a/hw/pci-bridge/cxl_root_port.c > +++ b/hw/pci-bridge/cxl_root_port.c > @@ -53,6 +53,7 @@ typedef struct CXLRootPort { > CPMUState cpmu; > MemoryRegion cpmu_registers; > PCIResReserve res_reserve; > + bool uio_capable; I'd bring these in with a patch that uses them. This whole thing is simple enough maybe just have it as part of a commit that uses the properties. > } CXLRootPort; > > #define TYPE_CXL_ROOT_PORT "cxl-rp" > diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c > index ef5480b116..dadad3e15c 100644 > --- a/hw/pci-bridge/cxl_upstream.c > +++ b/hw/pci-bridge/cxl_upstream.c > @@ -437,6 +437,8 @@ static const Property cxl_upstream_props[] = { > DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, > width, PCIE_LINK_WIDTH_16), > DEFINE_PROP_BOOL("x-256b-flit", CXLUpstreamPort, flitmode, false), > + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), > + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, false), > }; > > static void cxl_upstream_class_init(ObjectClass *oc, const void *data) > diff --git a/include/hw/pci-bridge/cxl_upstream_port.h > b/include/hw/pci-bridge/cxl_upstream_port.h > index d4186234c8..d23541e23a 100644 > --- a/include/hw/pci-bridge/cxl_upstream_port.h > +++ b/include/hw/pci-bridge/cxl_upstream_port.h > @@ -22,6 +22,7 @@ typedef struct CXLUpstreamPort { > PCIExpLinkSpeed speed; > PCIExpLinkWidth width; > bool flitmode; > + bool uio_capable; > > DOECap doe_cdat; > uint64_t sn;
