On 16/06/26 06:21PM, Jonathan Cameron wrote:
On Tue, 9 Jun 2026 16:28:32 +0530 Shrihari E S <[email protected]> wrote:Add Unordered IO (UIO) dependent property SVC to CXL ports (Root, Upstream and Downstream). The following properties are added to CXL ports: - x-uio-svc: Enable UIO traffic via SVC3 (mandatory path) - x-uio-svc-opt: Enable UIO traffic via SVC4 (optional path) Note: 256B flit mode property was already added in CXL ports, so reused it. Signed-off-by: Shrihari E S <[email protected]> Signed-off-by: Dongjoo Seo <[email protected]> --- static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index e82685d1ab..83fb5968b8 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -53,6 +53,7 @@ typedef struct CXLRootPort { CPMUState cpmu; MemoryRegion cpmu_registers; PCIResReserve res_reserve; + bool uio_capable;I'd bring these in with a patch that uses them. This whole thing is simple enough maybe just have it as part of a commit that uses the properties.
Hi Jonathan, Yeah sure will move this field to the patch that uses it. Thought it would be a prep patch for the patch that really uses this feature. Thanks,
} CXLRootPort;
