> -----Original Message-----
> From: Peter Maydell <[email protected]>
> Sent: 16 June 2026 20:10
> To: Shameer Kolothum Thodi <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; Nicolin Chen
> <[email protected]>; Nathan Chen <[email protected]>; Matt Ochs
> <[email protected]>; Jiandi An <[email protected]>; Jason Gunthorpe
> <[email protected]>; [email protected]; Krishnakant Jaju
> <[email protected]>; [email protected]
> Subject: Re: [PATCH v7 00/31] hw/arm/virt: Introduce Tegra241 CMDQV
> support for accelerated SMMUv3
>
> External email: Use caution opening links or attachments
>
>
> On Tue, 9 Jun 2026 at 12:27, Shameer Kolothum
> <[email protected]> wrote:
> >
> > Hi,
> >
> > Changes from v6:
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.
> kernel.org%2Fqemu-devel%2F20260601114221.457995-1-
> skolothumtho%40nvidia.com%2F&data=05%7C02%7Cskolothumtho%40nvi
> dia.com%7C85054cd29a1d4722ba0908decbdaea61%7C43083d15727340c
> 1b7db39efd9ccc17a%7C0%7C0%7C639172338322799010%7CUnknown%
> 7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAi
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdat
> a=L73ziLGdAYoHaufzjyIBUBafyDdhNnIE9EyaJbzJWjo%3D&reserved=0
> >
> > - Addressed v6 feedback and picked up R-by/T-by tags. Thanks!
> > - mmap the host VINTF Page0 at IOMMU_VIOMMU_ALLOC instead of on
> VINTF
> > enable (patch #14)
> > - Reset the per-VCMDQ Page0 cache when a queue is freed (patch #19)
> > - Distributed the reset teardown into the patches that introduce each
> > resource (patches #18, #21)
> > - Added a VCMDQ readiness helper and renamed the Page0 backing-pointer
> > helper to vintf_lvcmdq_ptr() (patches #18, #19)
> > - Trace the VCMDQ Page0 backing, hw vs cache (patch #19)
> > - Renamed patch #24 to reflect the changes accurately
> > - Updated the design and lifecycle documentation (patch #30)
> > - Based on top of Nathan's "Resolve AUTO properties" v6 series [0].
> >
> > Please find the complete branch here:
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Fshamiali2008%2Fqemu-master%2Ftree%2Fmaster-vcmdq-v7-
> ext&data=05%7C02%7Cskolothumtho%40nvidia.com%7C85054cd29a1d47
> 22ba0908decbdaea61%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C
> 0%7C639172338322871287%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU
> 1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIs
> IldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=uHKbMM0Gxk6t%2Bw7gRw
> M%2FiTcx9xuDNFKeaDDFZ48qfZA%3D&reserved=0
> >
> > Sanity tested on NVIDIA Grace. Further testing in progress.
> >
> > Feedback and testing are very welcome.
>
>
>
> > hw/arm/smmuv3-accel.h | 48 ++
> > hw/arm/tegra241-cmdqv.h | 384 +++++++++++
> > include/hw/arm/smmuv3.h | 3 +
> > include/hw/arm/virt.h | 1 +
> > include/system/iommufd.h | 17 +-
> > include/system/memory.h | 21 +
> > backends/iommufd.c | 64 ++
> > hw/arm/smmuv3-accel-stubs.c | 12 +
> > hw/arm/smmuv3-accel.c | 194 ++++--
> > hw/arm/smmuv3.c | 10 +
> > hw/arm/tegra241-cmdqv-stubs.c | 16 +
> > hw/arm/tegra241-cmdqv.c | 1119
> +++++++++++++++++++++++++++++++++
> > hw/arm/virt-acpi-build.c | 127 ++--
> > hw/arm/virt.c | 37 ++
> > hw/vfio/iommufd.c | 4 +-
> > hw/vfio/listener.c | 6 +
> > system/memory.c | 10 +
> > backends/trace-events | 4 +-
> > hw/arm/Kconfig | 5 +
> > hw/arm/meson.build | 2 +
> > hw/arm/trace-events | 11 +
> > hw/vfio/trace-events | 1 +
> > qemu-options.hx | 8 +
> > 23 files changed, 2024 insertions(+), 80 deletions(-)
> > create mode 100644 hw/arm/tegra241-cmdqv.h
> > create mode 100644 hw/arm/tegra241-cmdqv-stubs.c
> > create mode 100644 hw/arm/tegra241-cmdqv.c
>
> Hi -- I just noticed looking at this diffstat that it does not
> make any updates to the documentation to describe this
> new feature. Please could you add something (e.g. to
> docs/system/arm/virt.rst, or elsewhere if more appropriate)
> that describes whatever this new thing is and how to use it,
> in terms that make sense to somebody who isn't deeply immersed in
> the SMMU and this Nvidia specific bit of hardware ?
> You can do this as a followup patch, as I've already queued
> this series.
Thanks. We have this in qemu-options.hx(patch #31)
+ ``cmdqv=on|off|auto`` (default: auto)
+ Enable hardware Command Queue Virtualization (CMDQV) for the
+ SMMUv3 command queue. Currently only the NVIDIA Tegra241 CMDQV
+ implementation is supported.
We could add a subsection under "User-creatable SMMUv3 devices" in virt.rst
to add a bit more detail. I will send out a patch.
> Also, a bullet point for the Changelog giving the short
> summary of what the new thing is would be nice. This
> cover letter was too cryptic for me to be able to guess :-)
Maybe something like:
NVIDIA Tegra241 Hardware Command Queue Virtualisation (CMDQV) support is
now available via "-device arm-smmuv3,accel=on,cmdqv=on", giving each VM
dedicated hardware SMMUv3 command queues, improving performance.
Thanks,
Shameer
