Hi, I think I have seen this patch at least twice in the list o.O
It seems it has not been merged into master yet (@Michael, do you want me to send a rebased version?). https://patchew.org/QEMU/CAFFE2avrHDKZd5m7j3E3x5=F=pzn-3c9vzgwp3+9-avpwqn...@mail.gmail.com/ Thanks for the effort though ;) cmd On Mon, 2026-06-22 at 18:21 +0200, no92 wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > With the changes in c7b2e22bd957, the `pt` bit was set in the (wrong) > capability register, instead of the (correct) extended capability > register. > > Fixes: c7b2e22bd95710e404c393e9f563cfe7404220c1 ("hw/i386/x86-iommu: Remove > X86IOMMUState::pt_supported field") > Signed-off-by: no92 <[[email protected]](mailto:[email protected])> > --- > hw/i386/intel_iommu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 744cdfd2e6..d1af7a3135 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -4988,7 +4988,7 @@ static void vtd_cap_init(IntelIOMMUState *s) > { > X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); > > - s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT | > + s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | > VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_DRAIN | > VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits); > if (x86_iommu->dma_translation) { > @@ -4999,7 +4999,7 @@ static void vtd_cap_init(IntelIOMMUState *s) > s->cap |= VTD_CAP_SAGAW_48bit; > } > } > - s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; > + s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_PT; > > if (x86_iommu_ir_supported(x86_iommu)) { > s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; > -- > 2.54.0 >
