On 6/23/26 00:21, no92 wrote:
With the changes in c7b2e22bd957, the `pt` bit was set in the (wrong) capability register, instead of the (correct) extended capability register.Fixes: c7b2e22bd95710e404c393e9f563cfe7404220c1 ("hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field")
nit: c7b2e22bd957 12bits
Signed-off-by: no92 <[email protected]> --- hw/i386/intel_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Yi Liu <[email protected]>
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 744cdfd2e6..d1af7a3135 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4988,7 +4988,7 @@ static void vtd_cap_init(IntelIOMMUState *s) { X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);- s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT |+ s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_DRAIN | VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits); if (x86_iommu->dma_translation) { @@ -4999,7 +4999,7 @@ static void vtd_cap_init(IntelIOMMUState *s) s->cap |= VTD_CAP_SAGAW_48bit; } } - s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; + s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_PT;if (x86_iommu_ir_supported(x86_iommu)) {s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
