On 6/22/2026 5:52 PM, Pierrick Bouvier wrote:
On 6/22/2026 12:31 PM, Daniel Henrique Barboza wrote:
Hello,
This series looks scary but it's mostly trivial and mechanical work.
It is yet another attempt at fixing --disable-tcg. We have a recent
work sent to the ML [1] and we had Phil's attempt back in 2023 [2].
Phil's work didn't get merged and it's now too hard to rebase and
revive, the most recent attempt got misled into the 'what is common code
between TCG and KVM' dungeon.
After reviewing [1] I went ahead and look what other targets were doing
w.r.t their directory structure and comparing to RISC-V. In our case we
have a log going on in target/riscv:
$ ls target/riscv
Kconfig cpu_cfg.h fpu_helper.c machine.c
sbi_ecall_interface.h vector_internals.c
XVentanaCondOps.decode cpu_cfg_fields.h.inc gdbstub.c meson.build
tcg vector_internals.h
arch_dump.c cpu_helper.c helper.h mips_csr.c
th_csr.c xlrbr.decode
bitmanip_helper.c cpu_user.h insn16.decode monitor.c
time_helper.c xmips.decode
common-semi-target.c cpu_vendorid.h insn32.decode op_helper.c
time_helper.h xthead.decode
cpu-param.h crypto_helper.c insn_trans pmp.c
trace-events zce_helper.c
cpu-qom.h csr.c instmap.h pmp.h
trace.h
cpu.c csr.h internals.h pmu.c
translate.c
cpu.h debug.c kvm pmu.h
vcrypto_helper.c
cpu_bits.h debug.h m128_helper.c riscv-qmp-cmds.c
vector_helper.c
It is non-trivial to realize that most of this stuff is TCG specific.
Meanwhile our 'tcg' subdir is mostly empty:
$ ls target/riscv/tcg
meson.build tcg-cpu.c tcg-cpu.h
If we compare it with other targets, let's say loongarch:
$ ls target/loongarch/
Kconfig cpu-csr.h cpu-qom.h cpu_helper.c disas.c insns.decode
loongarch-qmp-cmds.c tcg translate.h
README cpu-mmu.h cpu.c csr.c gdbstub.c internals.h
machine.c trace-events vec.h
arch_dump.c cpu-param.h cpu.h csr.h helper.h kvm
meson.build trace.h
$
$ ls target/loongarch/tcg
constant_timer.c fpu_helper.c insn_trans meson.build tcg_cpu.c
tlb_helper.c vec_helper.c
csr_helper.c helper.h iocsr_helper.c op_helper.c tcg_loongarch.h
translate.c
It is straightforward to see which files are TCG exclusive and which
files are common to all accels.
And this is what we did here. The patches goes mostly as follows:
- move stuff to 'tcg' subdir. Most stuff is straighforward and is
manageable with a single patch. Other things required some logic to
go to either cpu.c or tcg-cpu;
- move TCG stuff to tcg-cpu.c;
- move common accel stuff to cpu.c. Usually from cpu_helper.c;
- filter TCG specific code in cpu.c and other files;
- trivial/assorted fixes in misc files that were needed to make
--disable-tcg work.
Patch 24 is taken from Zephyr Li to enable the CI for --disable-tcg.
Hopefully we won't break it anytime soon.
After this series we have --disable-tcg working and the following dir
structure:
$ ls target/riscv
Kconfig cpu.c cpu_vendorid.h internals.h
sbi_ecall_interface.h xlrbr.decode
XVentanaCondOps.decode cpu.h gdbstub.c kvm
tcg xmips.decode
arch_dump.c cpu_bits.h helper.h machine.c
time_helper.c xthead.decode
common-semi-target.c cpu_cfg.h insn16.decode meson.build
time_helper.h
cpu-param.h cpu_cfg_fields.h.inc insn32.decode monitor.c
trace-events
cpu-qom.h cpu_user.h instmap.h riscv-qmp-cmds.c
trace.h
$
$ ls target/riscv/tcg
bitmanip_helper.c csr.h insn_trans op_helper.c pmu.h
translate.c vector_internals.h
cpu_helper.c debug.c m128_helper.c pmp.c tcg-cpu.c
vcrypto_helper.c zce_helper.c
crypto_helper.c debug.h meson.build pmp.h tcg-cpu.h
vector_helper.c
csr.c fpu_helper.c mips_csr.c pmu.c th_csr.c
vector_internals.c
[1]
https://lore.kernel.org/qemu-devel/[email protected]/
[2] https://lore.kernel.org/qemu-devel/[email protected]/
Daniel Henrique Barboza (22):
target/riscv: move TCG only files to tcg subdir
target/riscv/machine.c: do not migrate pmp state with kvm
target/riscv: move pmp files to tcg subdir
target/riscv: make some riscv_sysemu_ops TCG only
target/riscv: move pmu.h to tcg subdir
target/riscv: move debug.h to tcg subdir
target/riscv: remove csr.h from kvm-cpu.c
target/riscv: move csr.h to tcg subdir
target/riscv: move custom_csrs logic to tcg-cpu.c
target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c
target/riscv: move valid_vm_* satp arrays to cpu.c
target/riscv: move some irq helpers to cpu.c
target/riscv: move riscv_cpu_claim_interrupts to cpu.c
target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
hw/riscv/riscv_hart.c isolate tcg only bits
target/riscv/gdbstub.c: isolate TCG only checks
target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
target/riscv/tcg: remove unused riscv_cpu_get_geilen()
target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
Zephyr Li (2):
target/riscv: Remove unused tcg/tcg.h include
gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
.gitlab-ci.d/crossbuilds.yml | 8 +
hw/intc/riscv_aclint.c | 8 +
hw/intc/riscv_imsic.c | 24 ++
hw/riscv/fdt-common.c | 52 +++
hw/riscv/riscv_hart.c | 4 +-
hw/riscv/virt.c | 1 -
include/hw/riscv/fdt-common.h | 1 +
target/riscv/cpu.c | 316 +++++++++++++++---
target/riscv/cpu.h | 19 +-
target/riscv/gdbstub.c | 10 +-
target/riscv/kvm/kvm-cpu.c | 1 -
target/riscv/machine.c | 15 +-
target/riscv/meson.build | 17 -
target/riscv/monitor.c | 4 +-
target/riscv/riscv-qmp-cmds.c | 2 +-
target/riscv/{ => tcg}/bitmanip_helper.c | 0
target/riscv/{ => tcg}/cpu_helper.c | 239 +------------
target/riscv/{ => tcg}/crypto_helper.c | 0
target/riscv/{ => tcg}/csr.c | 45 +--
target/riscv/{ => tcg}/csr.h | 6 +-
target/riscv/{ => tcg}/debug.c | 2 +-
target/riscv/{ => tcg}/debug.h | 0
target/riscv/{ => tcg}/fpu_helper.c | 0
.../insn_trans/trans_privileged.c.inc | 0
.../{ => tcg}/insn_trans/trans_rva.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
.../insn_trans/trans_rvzicfiss.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
.../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
.../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
.../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
.../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
.../insn_trans/trans_xventanacondops.c.inc | 0
.../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
target/riscv/{ => tcg}/m128_helper.c | 0
target/riscv/tcg/meson.build | 31 +-
target/riscv/{ => tcg}/mips_csr.c | 2 +-
target/riscv/{ => tcg}/op_helper.c | 2 +-
target/riscv/{ => tcg}/pmp.c | 2 +-
target/riscv/{ => tcg}/pmp.h | 0
target/riscv/{ => tcg}/pmu.c | 52 ---
target/riscv/{ => tcg}/pmu.h | 1 -
target/riscv/tcg/tcg-cpu.c | 30 +-
target/riscv/{ => tcg}/th_csr.c | 2 +-
target/riscv/{ => tcg}/translate.c | 0
target/riscv/{ => tcg}/vcrypto_helper.c | 0
target/riscv/{ => tcg}/vector_helper.c | 0
target/riscv/{ => tcg}/vector_internals.c | 0
target/riscv/{ => tcg}/vector_internals.h | 0
target/riscv/{ => tcg}/zce_helper.c | 0
target/riscv/time_helper.c | 33 +-
70 files changed, 495 insertions(+), 434 deletions(-)
rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
rename target/riscv/{ => tcg}/cpu_helper.c (92%)
rename target/riscv/{ => tcg}/crypto_helper.c (100%)
rename target/riscv/{ => tcg}/csr.c (99%)
rename target/riscv/{ => tcg}/csr.h (96%)
rename target/riscv/{ => tcg}/debug.c (99%)
rename target/riscv/{ => tcg}/debug.h (100%)
rename target/riscv/{ => tcg}/fpu_helper.c (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
rename target/riscv/{ => tcg}/m128_helper.c (100%)
rename target/riscv/{ => tcg}/mips_csr.c (99%)
rename target/riscv/{ => tcg}/op_helper.c (99%)
rename target/riscv/{ => tcg}/pmp.c (99%)
rename target/riscv/{ => tcg}/pmp.h (100%)
rename target/riscv/{ => tcg}/pmu.c (86%)
rename target/riscv/{ => tcg}/pmu.h (95%)
rename target/riscv/{ => tcg}/th_csr.c (99%)
rename target/riscv/{ => tcg}/translate.c (100%)
rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
rename target/riscv/{ => tcg}/vector_helper.c (100%)
rename target/riscv/{ => tcg}/vector_internals.c (100%)
rename target/riscv/{ => tcg}/vector_internals.h (100%)
rename target/riscv/{ => tcg}/zce_helper.c (100%)
It seems like series does not apply on top of master, would that be
possible to rebase it?
Oh, sorry. I forgot to mention that patches are based on alistair's
riscv-to-apply.next branch:
https://github.com/alistair23/qemu
Cheers,
Daniel
Regards,
Pierrick
