On 6/22/2026 6:04 PM, Philippe Mathieu-Daudé wrote:
On 22/6/26 21:31, Daniel Henrique Barboza wrote:
This function is related to Smrnmi and non-masked interrupts, firing up
interrupts via env->rnmip from riscv_cpu_local_irq_pending().
This is all TCG only code.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
---
target/riscv/cpu.c | 8 --------
target/riscv/tcg/tcg-cpu.c | 7 +++++++
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fef66557c2..0d0a704179 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu,
const RISCVCSR *csr_list)
}
}
}
+
+static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
+{
+ riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
Preferably inlining riscv_cpu_set_rnmi() here:
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Inlined. Thx!
+}
#endif
