From: Daniel Henrique Barboza <[email protected]> promote_load_fault() is missing the promotion of misaligned AMO load addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e. always_storeamo is true).
All other load AMO faults are already being covered. Cc: [email protected] Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise store/AMO fault") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503 Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Chao Liu <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit d85a4ec06a65ccdd5c7d0f00b3e6695fc14a547a) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59f6d00774..dc21c4ee44 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2218,6 +2218,9 @@ static target_ulong promote_load_fault(target_ulong orig_cause) case RISCV_EXCP_LOAD_PAGE_FAULT: return RISCV_EXCP_STORE_PAGE_FAULT; + + case RISCV_EXCP_LOAD_ADDR_MIS: + return RISCV_EXCP_STORE_AMO_ADDR_MIS; } /* if no promotion, return original cause */ -- 2.47.3
