From: Abhigyan Kumar <[email protected]>
Citing the RISC-V specification:
"The vector fixed-point rounding-mode register holds a two-bit
read-write rounding-mode field in the least-significant bits
(vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as
zeros."
QEMU wrote full value into env->vxrm causing read of upper bits too.
Used existing macros for bit-masking. Previous had a hard-coded value.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3470
Signed-off-by: Abhigyan Kumar <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
(cherry picked from commit 9f550a0b630672f4831d9115e66d208ed71cf252)
Signed-off-by: Michael Tokarev <[email protected]>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9d1ef159b5..a5c1143a7b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -955,7 +955,7 @@ static RISCVException write_vxrm(CPURISCVState *env, int
csrno,
#if !defined(CONFIG_USER_ONLY)
env->mstatus |= MSTATUS_VS;
#endif
- env->vxrm = val;
+ env->vxrm = val & (VCSR_VXRM >> VCSR_VXRM_SHIFT);
return RISCV_EXCP_NONE;
}
--
2.47.3
