From: Daniel Henrique Barboza <[email protected]>
The priv spec states the following about mstatus.MPV:
"The MPV bit (Machine Previous Virtualization Mode) is written by the
implementation whenever a trap is taken into M-mode."
And, about mstatus.GVA:
"Field GVA (Guest Virtual Address) is written by the implementation
whenever a trap is taken into M-mode."
Both are written during riscv_cpu_do_interrupt(). They're not supposed
to be written by userspace. As far as write_mstatus goes these fields
are read only. The same applies for mstatush.MPV/mstatush.GVA.
Fixes: 03dd405dd5 ("target/riscv: Support MSTATUS.MPV/GVA only when RVH is
enabled")
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
(cherry picked from commit 18645f19578955ec5ff2c40cd2c8753d6bc460c2)
Signed-off-by: Michael Tokarev <[email protected]>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a62b16feae..5e1b840087 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2014,9 +2014,6 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
}
if (xl != MXL_RV32 || env->debugger) {
- if (riscv_has_ext(env, RVH)) {
- mask |= MSTATUS_MPV | MSTATUS_GVA;
- }
if ((val & MSTATUS64_UXL) != 0) {
mask |= MSTATUS64_UXL;
}
@@ -2053,7 +2050,7 @@ static RISCVException write_mstatush(CPURISCVState *env,
int csrno,
target_ulong val)
{
uint64_t valh = (uint64_t)val << 32;
- uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0;
+ uint64_t mask = 0;
if (riscv_cpu_cfg(env)->ext_smdbltrp) {
mask |= MSTATUS_MDT;
--
2.47.3
