This introduces new forms of FCVTXX instructions which convert floating point to integer but place the results in SIMD & FP registers, and forms of the [SU]CVTF instructions which convert from integer to FP with a source in SIMD & FP registers. The logic for conversion and test values are otherwise the same as the versions which use general-purpose registers.
Signed-off-by: Jim MacArthur <[email protected]> --- Changes in v2: - New instructions are gated on FPRCVT flag - do_cvtf_simd removed; changes folded into do_cvtf_f - Some vector forms of instructions are now allowed in streaming mode (new patch) - Tests restructured to avoid the duplication of fcvt.ref - docs/system/arm/emulation.rst updated to indicate FPRCVT support - linux-user/aarch64/elfload.c now reports FPRCVT - Link to v1: https://lore.kernel.org/qemu-devel/[email protected] --- Jim MacArthur (6): target/arm/tcg: Implement new instructions for FPRCVT target/arm/tcg: Allow vector FP conversions with FPRCVT target/arm/tcg/cpu64.c: Add FEAT_FPRCVT to cpu_max linux-user/aarch64/elfload.c: Add FPRCVT docs/system/arm: Add FEAT_FPRCVT to A-profile support tests/tcg/arm: Tests for new FPRCVT instructions docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/cpu-features.h | 5 +++ target/arm/tcg/a64.decode | 15 +++++++ target/arm/tcg/cpu64.c | 1 + target/arm/tcg/translate-a64.c | 89 ++++++++++++++++++++++++++++++++++----- tests/tcg/aarch64/Makefile.target | 14 +++++- tests/tcg/arm/fcvt.c | 7 +++ 8 files changed, 122 insertions(+), 11 deletions(-) --- base-commit: b83371668192a705b878e909c5ae9c1233cbd5fb change-id: 20260618-jmac-fprcvt-1554d4c80bc8 Best regards, -- Jim MacArthur <[email protected]>
