+ adding people from ./scripts/get_maintainer.pl in cc On 26/06/17 12:31AM, Kirill A. Korinsky wrote: > OpenBSD/powernv programs PTCR for LPID 0 with a partition > table size exponent one smaller than QEMU's existing ISA v3.0 > interpretation. Try QEMU's existing PATS interpretation first, > then fall back to the OpenBSD LPID 0 form; nonzero LPIDs keep > the old behaviour. > > The PSI model now exposes POWER9 IRQ level and pending status > registers, and keeps both updated while delivering through the > existing XIVE LSI source. This lets guests that select the > POWER9 PSI LSI IRQ method continue to receive LPC interrupts. > > The blast radius is probably minimal: the partition table > fallback is limited to bare metal LPID 0 after the original > lookup fails, while the PSI change only touches POWER9 PSI > state and reuses the existing delivery path.
Thanks for the interesting change Kirill ! Will be nice to have OpenBSD boot in PowerNV. > > Signed-off-by: Kirill A. Korinsky <[email protected]> > @@ -817,18 +819,15 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = { > static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) > { > PnvPsi *psi = opaque; > - uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; > + uint64_t irq_bit = PPC_BIT(irq); > > - if (irq_method & PSIHB9_IRQ_METHOD) { > - qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); > - return; > - } is it required to remove this check ? afais, irq_method isn't having this bit set by openbsd too. > <...snip...> > /* Calculate number of entries */ > - pats = 1ull << (pats + 12 - 4); > - if (pats <= lpid) { > + entries = table_size / sizeof(*entry); nit: previously sizeof(*entry) == 1<<4 = 16 bytes. just to be extra cautious, should we have __packed in ppc_v3_pate_t, can compilers increase the size of the struct any arch ? i can't think of one just being extra cautious > + if (entries <= lpid) { > return false; > } > > @@ -45,3 +47,24 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, > ppc_v3_pate_t *entry) > entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); > return true; > } > + > +bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t > *entry) > +{ > + uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; > + > + /* > + * Keep the existing ISA v3.0 PATS interpretation first. OpenBSD/powernv > + * uses the PATSIZE value it writes to PTCR as one exponent smaller, and > it > + * only needs that interpretation for the bare metal LPID 0 table. > + */ > + if (ppc64_v3_get_pate_from_size(cpu, lpid, entry, 1ull << (pats + 12))) { > + return true; > + } > + > + if (lpid == 0) { > + return ppc64_v3_get_pate_from_size(cpu, lpid, entry, > + 1ull << (pats + 11)); any reason openbsd needs to populate ptcr this way ? thanks for adding a testcase too ! - Aditya G > 2.54.0
