On Wed, Jun 17, 2026 at 5:04 AM Kuan-Wei Chiu <[email protected]> wrote:
>
> Add the Sophgo CV1800B SoC, which is the heart of the Milk-V Duo board.
>
> The SoC features a T-Head C906 CPU along with integrated PLIC, CLINT,
> and dw8250 UART. The memory map and interrupts are configured according
> to the CV1800B datasheet. [1]
>
> Several peripheral blocks are included as unimplemented devices to
> ensure that drivers can probe successfully without causing errors
> during boot.
>
> Link: https://github.com/milkv-duo/duo-files/tree/main/duo/datasheet [1]
> Signed-off-by: Kuan-Wei Chiu <[email protected]>
> ---
> hw/riscv/Kconfig | 8 ++
> hw/riscv/cv1800b.c | 168 +++++++++++++++++++++++++++++++++++++
> hw/riscv/meson.build | 2 +
> include/hw/riscv/cv1800b.h | 52 ++++++++++++
> 4 files changed, 230 insertions(+)
> create mode 100644 hw/riscv/cv1800b.c
> create mode 100644 include/hw/riscv/cv1800b.h
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 54e41a6afc..299baed4a8 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -149,3 +149,11 @@ config K230
> select SERIAL_MM
> select UNIMP
> select K230_WDT
> +
> +config SOPHGO_CV1800B
> + bool
> + depends on RISCV64
> + select RISCV_ACLINT
> + select SIFIVE_PLIC
> + select SOPHGO_CV1800B_CLK
> + select DW8250
> diff --git a/hw/riscv/cv1800b.c b/hw/riscv/cv1800b.c
> new file mode 100644
> index 0000000000..c6749e1202
> --- /dev/null
> +++ b/hw/riscv/cv1800b.c
> @@ -0,0 +1,168 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Sophgo CV1800B SoC
> + *
> + * Copyright (c) 2026 Kuan-Wei Chiu <[email protected]>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/riscv/cv1800b.h"
> +#include "hw/core/qdev-properties.h"
> +#include "target/riscv/cpu-qom.h"
> +#include "system/system.h"
> +#include "hw/char/serial.h"
> +#include "hw/intc/riscv_aclint.h"
> +#include "system/address-spaces.h"
> +#include "hw/intc/sifive_plic.h"
> +#include "target/riscv/cpu.h"
> +#include "hw/riscv/boot.h"
> +#include "hw/sd/sdhci.h"
> +#include "hw/misc/unimp.h"
> +
> +const MemMapEntry cv1800b_memmap[] = {
> + [CV1800B_DEV_TOP_MISC] = { 0x03000000, 0x1000 },
> + [CV1800B_DEV_PINMUX] = { 0x03001000, 0x1000 },
> + [CV1800B_DEV_CLK] = { 0x03002000, 0x1000 },
> + [CV1800B_DEV_RST] = { 0x03003000, 0x1000 },
> + [CV1800B_DEV_WDT] = { 0x03010000, 0x1000 },
> + [CV1800B_DEV_GPIO] = { 0x03020000, 0x4000 },
> + [CV1800B_DEV_UART0] = { 0x04140000, 0x10000 },
> + [CV1800B_DEV_SD0] = { 0x04310000, 0x10000 },
> + [CV1800B_DEV_ROM] = { 0x04400000, 0x10000 },
> + [CV1800B_DEV_RTC_GPIO] = { 0x05021000, 0x1000 },
> + [CV1800B_DEV_RTC_IO] = { 0x05027000, 0x1000 },
> + [CV1800B_DEV_PLIC] = { 0x70000000, 0x4000000 },
> + [CV1800B_DEV_CLINT] = { 0x74000000, 0x10000 },
> + [CV1800B_DEV_DRAM] = { 0x80000000, 0x0 },
> +};
> +
> +static void cv1800b_soc_instance_init(Object *obj)
> +{
> + CV1800BSoCState *s = CV1800B_SOC(obj);
> +
> + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
> + object_initialize_child(obj, "clk", &s->clk, TYPE_CV1800B_CLK);
> +}
> +
> +static void cv1800b_soc_realize(DeviceState *dev, Error **errp)
> +{
> + CV1800BSoCState *s = CV1800B_SOC(dev);
> + MachineState *ms = MACHINE(qdev_get_machine());
> + uint32_t num_harts = ms->smp.cpus;
> + MemoryRegion *system_memory = get_system_memory();
> + char *plic_hart_config;
> + DeviceState *uart, *sdhci;
> +
> + qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts);
> + qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0);
> + qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type",
> TYPE_RISCV_CPU_THEAD_C906);
> +
> + qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec",
> + cv1800b_memmap[CV1800B_DEV_ROM].base);
> +
> + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
> +
> + memory_region_init_rom(&s->rom, OBJECT(dev), "cv1800b.rom",
> + cv1800b_memmap[CV1800B_DEV_ROM].size,
> &error_fatal);
> + memory_region_add_subregion(system_memory,
> + cv1800b_memmap[CV1800B_DEV_ROM].base,
> &s->rom);
> +
> + riscv_aclint_swi_create(cv1800b_memmap[CV1800B_DEV_CLINT].base,
> + 0, num_harts, false);
> + riscv_aclint_mtimer_create(cv1800b_memmap[CV1800B_DEV_CLINT].base +
> + RISCV_ACLINT_SWI_SIZE,
> + RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
> + 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
> + RISCV_ACLINT_DEFAULT_MTIME,
> + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
> +
> + plic_hart_config = riscv_plic_hart_config_string(num_harts);
> + s->plic = sifive_plic_create(
> + cv1800b_memmap[CV1800B_DEV_PLIC].base,
> + plic_hart_config,
> + num_harts,
> + 0,
> + CV1800B_PLIC_NUM_SOURCES,
> + CV1800B_PLIC_NUM_PRIORITIES,
> + 0x0,
> + 0x1000,
> + 0x2000,
> + 0x80,
> + 0x200000,
> + 0x1000,
> + cv1800b_memmap[CV1800B_DEV_PLIC].size);
> +
> + g_free(plic_hart_config);
> +
> + uart = qdev_new("dw8250");
We generally want to create the device in the init function and then
realise it here, like you do with the clock for example
Alistair
> + qdev_prop_set_uint8(uart, "regshift", 2);
> + qdev_prop_set_chr(uart, "chardev", serial_hd(0));
> + sysbus_realize(SYS_BUS_DEVICE(uart), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(uart), 0,
> cv1800b_memmap[CV1800B_DEV_UART0].base);
> + sysbus_connect_irq(SYS_BUS_DEVICE(uart), 0,
> + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_UART0_IRQ));
> +
> + sdhci = qdev_new(TYPE_SYSBUS_SDHCI);
> + qdev_prop_set_uint8(sdhci, "sd-spec-version", 3);
> + qdev_prop_set_uint64(sdhci, "capareg", 0x056900b9);
> + sysbus_realize(SYS_BUS_DEVICE(sdhci), &error_fatal);
> + sysbus_mmio_map(SYS_BUS_DEVICE(sdhci), 0,
> cv1800b_memmap[CV1800B_DEV_SD0].base);
> + sysbus_connect_irq(SYS_BUS_DEVICE(sdhci), 0,
> + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_SD0_IRQ));
> +
> + sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_fatal);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0,
> + cv1800b_memmap[CV1800B_DEV_CLK].base);
> +
> + create_unimplemented_device("cv1800b.top_misc",
> + cv1800b_memmap[CV1800B_DEV_TOP_MISC].base,
> + cv1800b_memmap[CV1800B_DEV_TOP_MISC].size);
> +
> + create_unimplemented_device("cv1800b.pinmux",
> + cv1800b_memmap[CV1800B_DEV_PINMUX].base,
> + cv1800b_memmap[CV1800B_DEV_PINMUX].size);
> +
> + create_unimplemented_device("cv1800b.rst",
> + cv1800b_memmap[CV1800B_DEV_RST].base,
> + cv1800b_memmap[CV1800B_DEV_RST].size);
> +
> + create_unimplemented_device("cv1800b.wdt",
> + cv1800b_memmap[CV1800B_DEV_WDT].base,
> + cv1800b_memmap[CV1800B_DEV_WDT].size);
> +
> + create_unimplemented_device("cv1800b.gpio0_3",
> + cv1800b_memmap[CV1800B_DEV_GPIO].base,
> + cv1800b_memmap[CV1800B_DEV_GPIO].size);
> +
> + create_unimplemented_device("cv1800b.rtc_gpio",
> + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].base,
> + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].size);
> +
> + create_unimplemented_device("cv1800b.rtc_io",
> + cv1800b_memmap[CV1800B_DEV_RTC_IO].base,
> + cv1800b_memmap[CV1800B_DEV_RTC_IO].size);
> +}
> +
> +static void cv1800b_soc_class_init(ObjectClass *oc, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = cv1800b_soc_realize;
> + dc->user_creatable = false;
> +}
> +
> +static const TypeInfo cv1800b_soc_type_info = {
> + .name = TYPE_CV1800B_SOC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(CV1800BSoCState),
> + .instance_init = cv1800b_soc_instance_init,
> + .class_init = cv1800b_soc_class_init,
> +};
> +
> +static void cv1800b_soc_register_types(void)
> +{
> + type_register_static(&cv1800b_soc_type_info);
> +}
> +
> +type_init(cv1800b_soc_register_types)
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index b70a054579..6c242d77da 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -19,4 +19,6 @@ riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true:
> files('cps.c'))
> riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
> riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c'))
>
> +riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c'))
> +
> hw_arch += {'riscv': riscv_ss}
> diff --git a/include/hw/riscv/cv1800b.h b/include/hw/riscv/cv1800b.h
> new file mode 100644
> index 0000000000..a214f7a9f6
> --- /dev/null
> +++ b/include/hw/riscv/cv1800b.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Sophgo CV1800B SoC
> + *
> + * Copyright (c) 2026 Kuan-Wei Chiu <[email protected]>
> + */
> +
> +#ifndef HW_RISCV_CV1800B_H
> +#define HW_RISCV_CV1800B_H
> +
> +#include "hw/core/boards.h"
> +#include "hw/riscv/riscv_hart.h"
> +#include "hw/misc/cv1800b_clk.h"
> +
> +#define TYPE_CV1800B_SOC "cv1800b-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(CV1800BSoCState, CV1800B_SOC)
> +
> +struct CV1800BSoCState {
> + DeviceState parent_obj;
> +
> + RISCVHartArrayState cpus;
> + MemoryRegion rom;
> + DeviceState *plic;
> + CV1800BClkState clk;
> +};
> +
> +#define CV1800B_PLIC_NUM_SOURCES 136
> +#define CV1800B_PLIC_NUM_PRIORITIES 31
> +
> +#define CV1800B_UART0_IRQ 44
> +#define CV1800B_SD0_IRQ 36
> +
> +enum {
> + CV1800B_DEV_TOP_MISC,
> + CV1800B_DEV_PINMUX,
> + CV1800B_DEV_CLK,
> + CV1800B_DEV_RST,
> + CV1800B_DEV_WDT,
> + CV1800B_DEV_GPIO,
> + CV1800B_DEV_UART0,
> + CV1800B_DEV_SD0,
> + CV1800B_DEV_ROM,
> + CV1800B_DEV_RTC_GPIO,
> + CV1800B_DEV_RTC_IO,
> + CV1800B_DEV_PLIC,
> + CV1800B_DEV_CLINT,
> + CV1800B_DEV_DRAM,
> +};
> +
> +extern const MemMapEntry cv1800b_memmap[];
> +
> +#endif
> --
> 2.54.0.1136.gdb2ca164c4-goog
>
>
