On Wed, 17 Jun 2026 at 04:31, Kuan-Wei Chiu <[email protected]> wrote:
> diff --git a/hw/riscv/cv1800b.c b/hw/riscv/cv1800b.c > new file mode 100644 > index 0000000000..c6749e1202 > --- /dev/null > +++ b/hw/riscv/cv1800b.c > @@ -0,0 +1,168 @@ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* > + * Sophgo CV1800B SoC > + * > + * Copyright (c) 2026 Kuan-Wei Chiu <[email protected]> > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "hw/riscv/cv1800b.h" > +#include "hw/core/qdev-properties.h" > +#include "target/riscv/cpu-qom.h" > +#include "system/system.h" > +#include "hw/char/serial.h" Unused? > +#include "hw/intc/riscv_aclint.h" > +#include "system/address-spaces.h" > +#include "hw/intc/sifive_plic.h" > +#include "target/riscv/cpu.h" > +#include "hw/riscv/boot.h" > +#include "hw/sd/sdhci.h" > +#include "hw/misc/unimp.h" > + > +static void cv1800b_soc_instance_init(Object *obj) > +{ > + CV1800BSoCState *s = CV1800B_SOC(obj); > + > + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); > + object_initialize_child(obj, "clk", &s->clk, TYPE_CV1800B_CLK); > +} > + > +static void cv1800b_soc_realize(DeviceState *dev, Error **errp) > +{ > + CV1800BSoCState *s = CV1800B_SOC(dev); > + MachineState *ms = MACHINE(qdev_get_machine()); > + uint32_t num_harts = ms->smp.cpus; > + MemoryRegion *system_memory = get_system_memory(); > + char *plic_hart_config; > + DeviceState *uart, *sdhci; > + > + qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts); > + qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0); > + qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type", > TYPE_RISCV_CPU_THEAD_C906); > + > + qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec", > + cv1800b_memmap[CV1800B_DEV_ROM].base); These could go in cv1800b_soc_instance_init. I think num-harts can stay here, as it relies on the machine details. > + > + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); > +
