The stream table base address needs to be aligned to its size. With FMT == 0, the spec says the linear stream table base address musst have ADDR[LOG2SIZE + 5:0] = 0. STE are 64B
With FMT == 1, ADDR[MAX(5, (LOG2SIZE - SPLIT - 1 + 3)):0] = 0. L1 descriptors are 8B. MAKE_64BIT_MASK() second argument is a size and not a shift, so there is an off-by-one computation. Signed-off-by: Eric Auger <[email protected]> --- hw/arm/smmuv3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 5e5a6a960c9..38aba9c0af9 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -664,7 +664,7 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { dma_addr_t addr, strtab_base; uint32_t log2size; - int strtab_size_shift; + int strtab_size; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -685,9 +685,9 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) * Align strtab base address to table size. For this purpose, assume it * is not bounded by SMMU_IDR1_SIDSIZE. */ - strtab_size_shift = MAX(5, (int)log2size - s->sid_split - 1 + 3); + strtab_size = MAX(6, (int)log2size - s->sid_split + 3); strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & - ~MAKE_64BIT_MASK(0, strtab_size_shift); + ~MAKE_64BIT_MASK(0, strtab_size); l1_ste_offset = sid >> s->sid_split; l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); @@ -729,9 +729,9 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) } addr = l2ptr + l2_ste_offset * sizeof(*ste); } else { - strtab_size_shift = log2size + 5; + strtab_size = log2size + 6; strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & - ~MAKE_64BIT_MASK(0, strtab_size_shift); + ~MAKE_64BIT_MASK(0, strtab_size); addr = strtab_base + sid * sizeof(*ste); } -- 2.53.0
