> -----Original Message-----
> From: Eric Auger <[email protected]>
> Sent: 01 July 2026 10:12
> To: [email protected]; [email protected]; qemu-
> [email protected]; [email protected]; [email protected];
> [email protected]; Shameer Kolothum Thodi
> <[email protected]>; Nicolin Chen <[email protected]>; Nathan
> Chen <[email protected]>
> Subject: [PATCH v2 5/5] hw/arm/smmuv3: Enforce alignment of L2Ptr
> according to the span
>
> External email: Use caution opening links or attachments
>
>
> Spec says: Bits L2Ptr[N:0] are treated as 0 by the SMMU, where N == 5 + (Span
> - 1).
>
> Let's enforce this alignment.
>
> Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Shameer Kolothum <[email protected]>
Thanks,
Shameer
> ---
> hw/arm/smmuv3.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index
> f694f832598..7eb2c59d9eb 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -728,6 +728,8 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid,
> STE *ste, SMMUEventInfo *event)
>
> max_l2_ste = (1 << span) - 1;
> l2ptr = l1std_l2ptr(&l1std);
> +
> + l2ptr &= ~MAKE_64BIT_MASK(0, 6 + (span - 1));
> trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset,
> l2ptr, l2_ste_offset, max_l2_ste);
> if (l2_ste_offset > max_l2_ste) {
> --
> 2.53.0
