On Sat, 6 Jun 2026, Chad Jablonski wrote:
When the CCE engine is enabled, real r128 hardware ignores any MMIO writes to
GUI registers (0x1400-0x1fff range). Writes made by the CCE engine are
not affected by this.
Testing on r100 shows that this behavior is specific to r128.
Tested and validated against a Rage 128 Pro Ultra (PCI 1002:5446) and
Radeon QY (RV100) (PCI 1002:5159).
Signed-off-by: Chad Jablonski <[email protected]>
---
hw/display/ati.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index e1ba64747b..582c646a3d 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -1183,6 +1183,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,
if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
}
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF &&
+ s->cce.buffer_mode && addr >= 0x1400 && addr <= 0x1fff) {
Should this go to ati_r128_mm_write then if we decided to have chip
specific functions? I still wonder if keeping the ifs would be simpler.
Regards,
BALATON Zoltan
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ati_mm_write: wrote 0x%"PRIx64" to gui register "
+ "0x%"PRIx64" while cce engine enabled, ignored.\n",
+ data, addr);
+ return;
+ }
+
switch (addr) {
case MM_INDEX:
s->regs.mm_index = data & ~3;
