This patch adds support to disassemble Zvfofp8min instructions.
Reviewed-by: Chao Liu <[email protected]>
Signed-off-by: Max Chou <[email protected]>
---
disas/riscv.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7f1b262773..bcda21fb62 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -990,6 +990,9 @@ typedef enum {
rv_op_cbo_flush = 958,
rv_op_cbo_zero = 959,
rv_op_mnret = 960,
+ rv_op_vfncvtbf16_sat_f_f_w = 961,
+ rv_op_vfncvt_f_f_q = 962,
+ rv_op_vfncvt_sat_f_f_q = 963,
} rv_op;
/* register names */
@@ -2260,11 +2263,14 @@ const rv_opcode_data rvi_opcode_data[] = {
rv_op_sspush, 0 },
{ "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
rv_op_sspopchk, 0 },
- { "cbo.inval", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "cbo.inval", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
+ { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
+ { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
+ { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
+ { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -3660,7 +3666,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa
isa)
case 21: op = rv_op_vfncvt_rod_f_f_w; break;
case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
+ case 25: op = rv_op_vfncvt_f_f_q; break;
+ case 27: op = rv_op_vfncvt_sat_f_f_q; break;
case 29: op = rv_op_vfncvtbf16_f_f_w; break;
+ case 31: op = rv_op_vfncvtbf16_sat_f_f_w; break;
}
break;
case 19:
--
2.55.0
