On Tue, Jul 7, 2026 at 7:11 PM <[email protected]> wrote:
>
> From: Frank Chang <[email protected]>
>
> Support the true Zicclsm extension so that we can trap misaligned accesses
> when Zicclsm is disabled.
>
> To enable/disable Zicclsm, simply set zicclsm=[true|false], e.g.:
> -cpu rv64,zicclsm=[true|false]
>
> QEMU will raise a misaligned load/store exception when executing misaligned
> load/store instructions if Zicclsm is disabled.
>
> Changelog:
> v4:
> * Align ROM reset vector data at 8-byte aligned offsets.
> v3:
> * Enable Zicclsm for the compatible CPUs.
> * Rebase to the latest riscv-to-apply.next.
> v2:
> * Use (size_memop(size) | mo_endian_env(env)) to calculate MemOp.
> * Use (log2_esz << MO_ASHIFT) to calculate aligment MemOp for
> vector load/store whole register instructions.
>
> Frank Chang (6):
> target/riscv: Add Zicclsm CPU option
> target/riscv: Support raising misaligned exceptions for scalar
> loads/stores
> target/riscv: Support raising misaligned exceptions for vector
> loads/stores
> target/riscv: Enable Zicclsm for the compatible CPUs
> hw/riscv: sifive_u: Align ROM reset vector data
> target/riscv: Update Zicclsm ISA string and expose it as a CPU
> property
Hmmm.... Still seeing failures
556/556 qemu:func-quick+func-riscv64 / func-riscv64-opensbi
TIMEOUT 90.02s killed by signal 15 SIGTERM
>>> LD_LIBRARY_PATH=/var/mnt/scratch/alistair/software/qemu/build/contrib/plugins:/var/mnt/scratch/alistair/software/qemu/build/tests/tcg/plugins
>>> MSAN_OPTIO
NS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1
QEMU_TEST_QEMU_BINARY=/var/mnt/scratch/alistair/software/qemu/build/qemu-system-riscv
64 RUST_BACKTRACE=1
MESON_BUILD_ROOT=/var/mnt/scratch/alistair/software/qemu/build
UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stac
ktrace=1 ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1
MESON_TEST_ITERATION=1 MALLOC_PERTURB_=7
QEMU_TEST_QEMU_IMG=/var/mnt/scratch/alistair
/software/qemu/build/qemu-img QEMU_TEST_GDB=/usr/bin/gdb
PYTHONPATH=/var/mnt/scratch/alistair/software/qemu/python:/var/mnt/scratch/alistair/software/qemu/t
ests/functional
/var/mnt/scratch/alistair/software/qemu/build/pyvenv/bin/python3
/var/mnt/scratch/alistair/software/qemu/tests/functional/riscv64/test_opens
bi.py
Summary of Failures:
556/556 qemu:func-quick+func-riscv64 / func-riscv64-opensbi
TIMEOUT 90.02s killed by signal 15 SIGTERM
Alistair
>
> hw/riscv/sifive_u.c | 11 +++--
> target/riscv/cpu.c | 9 +++-
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/insn_trans/trans_rvi.c.inc | 6 +++
> target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++--
> target/riscv/vector_helper.c | 65 +++++++++++++++++++------
> 6 files changed, 87 insertions(+), 24 deletions(-)
>
> --
> 2.43.0
>
>
