From: Daniel Henrique Barboza <[email protected]> These satp arrays are used internally in both csr.c and in cpu.c. csr.c is going to be moved to the TCG subdir in the next patch, and we want the satp logic to be available for KVM with --disable-tcg builds.
Move these arrays to cpu.c to keep them available for KVM with --disable-tcg. Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 2 -- target/riscv/csr.h | 3 +++ target/riscv/cpu.c | 13 +++++++++++++ target/riscv/csr.c | 12 ------------ 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bdd28d329b..82362ef8d8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -968,8 +968,6 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); -extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; - void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); diff --git a/target/riscv/csr.h b/target/riscv/csr.h index c791260f83..66ec9546ed 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -72,6 +72,9 @@ enum { CSR_TABLE_SIZE = 0x1000 }; +/* valid_vm_* arrays are shared with KVM via cpu.c */ +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7664e686fa..cae4e96232 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -65,6 +65,19 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, #define BYTE(x) (x) #endif +/* SATP bits that are shared between TCG and KVM */ +const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true +}; + +const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true +}; + bool riscv_cpu_is_32bit(RISCVCPU *cpu) { return riscv_cpu_mxl(&cpu->env) == MXL_RV32; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7168a4dc12..7818d81fb0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1875,18 +1875,6 @@ static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS; static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; -const bool valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = true, - [VM_1_10_SV32] = true -}; - -const bool valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = true, - [VM_1_10_SV39] = true, - [VM_1_10_SV48] = true, - [VM_1_10_SV57] = true -}; - /* Machine Information Registers */ static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) -- 2.54.0
