From: Daniel Henrique Barboza <[email protected]> After KVM is no longer reliant on csr.h move it to the TGC only land.
Signed-off-by: Daniel Henrique Barboza <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/{ => tcg}/csr.h | 0 target/riscv/cpu.c | 2 +- target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 2 +- target/riscv/riscv-qmp-cmds.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/mips_csr.c | 2 +- target/riscv/tcg/op_helper.c | 2 +- target/riscv/tcg/pmp.c | 2 +- target/riscv/tcg/th_csr.c | 2 +- 10 files changed, 9 insertions(+), 9 deletions(-) rename target/riscv/{ => tcg}/csr.h (100%) diff --git a/target/riscv/csr.h b/target/riscv/tcg/csr.h similarity index 100% rename from target/riscv/csr.h rename to target/riscv/tcg/csr.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba75c0de39..c5b03847bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -24,7 +24,7 @@ #include "qemu/guest-random.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "internals.h" #include "qapi/error.h" #include "qapi/visitor.h" diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a2bbaf7f07..f0a5e0d86f 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -21,7 +21,7 @@ #include "gdbstub/helpers.h" #include "cpu.h" #include "internals.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" struct TypeSize { const char *gdb_type; diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7aacd1d89c..f8042db9cd 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -22,7 +22,7 @@ #include "qemu/ctype.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index b94e8391ed..2647deef91 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -35,7 +35,7 @@ #include "system/tcg.h" #include "cpu-qom.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 9c7e9d0e4b..36f2004bc5 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" diff --git a/target/riscv/tcg/mips_csr.c b/target/riscv/tcg/mips_csr.c index 609718f288..884030e91d 100644 --- a/target/riscv/tcg/mips_csr.c +++ b/target/riscv/tcg/mips_csr.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" /* Static MIPS CSR state storage */ static struct { diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 6d4849b135..ba3c7da375 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "internals.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index d93563c36b..41b55519a8 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -23,7 +23,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "trace.h" #include "exec/cputlb.h" #include "exec/page-protection.h" diff --git a/target/riscv/tcg/th_csr.c b/target/riscv/tcg/th_csr.c index 431f4cc286..e6f642991c 100644 --- a/target/riscv/tcg/th_csr.c +++ b/target/riscv/tcg/th_csr.c @@ -22,7 +22,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" /* Extended M-mode control registers of T-Head */ #define CSR_TH_MXSTATUS 0x7c0 -- 2.54.0
