Add LVZ CSR number and bit-field definitions for guest status, configuration, interrupt, timer and guest TLB registers, preparing the architectural constants needed by later LVZ CPU state, CSR and TCG implementation patches.
Signed-off-by: SignKirigami <[email protected]> Signed-off-by: Hengyu Yu <[email protected]> --- target/loongarch/cpu-csr.h | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index d860417af2..4b0bb4d2e5 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -180,11 +180,13 @@ FIELD(CSR_TLBREHI_64, VPPN, 13, 35) #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ FIELD(CSR_TLBRPRMD, PPLV, 0, 2) FIELD(CSR_TLBRPRMD, PIE, 2, 1) +FIELD(CSR_TLBRPRMD, PGM, 3, 1) FIELD(CSR_TLBRPRMD, PWE, 4, 1) /* Machine Error CSRs */ #define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */ FIELD(CSR_MERRCTL, ISMERR, 0, 1) +FIELD(CSR_MERRCTL, PGM, 5, 1) #define LOONGARCH_CSR_MERRINFO1 0x91 #define LOONGARCH_CSR_MERRINFO2 0x92 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */ @@ -224,4 +226,44 @@ FIELD(CSR_DBG, ECODE, 16, 6) #define LOONGARCH_CSR_DERA 0x501 /* Debug era */ #define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */ +/* LVZ (LoongArch Virtualization) CSRs */ +#define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */ +FIELD(CSR_GSTAT, VM, 0, 1) +FIELD(CSR_GSTAT, PVM, 1, 1) +FIELD(CSR_GSTAT, GIDBIT, 4, 6) +FIELD(CSR_GSTAT, GID, 16, 8) + +#define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ +FIELD(CSR_GCFG, MATP, 0, 4) +FIELD(CSR_GCFG, MATC, 4, 2) +FIELD(CSR_GCFG, TOPIP, 6, 1) +FIELD(CSR_GCFG, TOPI, 7, 1) +FIELD(CSR_GCFG, TOTIP, 8, 1) +FIELD(CSR_GCFG, TOTI, 9, 1) +FIELD(CSR_GCFG, TOEP, 10, 1) +FIELD(CSR_GCFG, TOE, 11, 1) +FIELD(CSR_GCFG, TOPP, 12, 1) +FIELD(CSR_GCFG, TOP, 13, 1) +FIELD(CSR_GCFG, TOHUP, 14, 1) +FIELD(CSR_GCFG, TOHU, 15, 1) +FIELD(CSR_GCFG, TOCIP, 16, 4) +FIELD(CSR_GCFG, TOCI, 20, 2) +FIELD(CSR_GCFG, GPMP, 23, 1) +FIELD(CSR_GCFG, GPMNUM, 24, 3) + +#define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt config */ +FIELD(CSR_GINTC, HWIS, 0, 8) +FIELD(CSR_GINTC, HWIP, 8, 8) +FIELD(CSR_GINTC, HWIC, 16, 8) + +#define LOONGARCH_CSR_GCNTC 0x53 /* Guest counter compensation */ + +#define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */ +FIELD(CSR_GTLBC, GMTLBSZ, 0, 6) +FIELD(CSR_GTLBC, USETGID, 12, 1) +FIELD(CSR_GTLBC, TOTI, 13, 1) +FIELD(CSR_GTLBC, TGID, 16, 8) + +#define LOONGARCH_CSR_TRGP 0x16 /* Trapped guest physical address */ + #endif /* LOONGARCH_CPU_CSR_H */ -- 2.52.0
