Add the LVZ availability predicate, guest-mode translation context state and HW_FLAGS_GUEST_MODE translation block flag so later TCG patches can distinguish host and guest execution without mixing translator metadata with instruction behavior.
Signed-off-by: SignKirigami <[email protected]> Signed-off-by: Hengyu Yu <[email protected]> --- target/loongarch/translate.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 8aa8325dc6..257c3bbddd 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -24,6 +24,7 @@ #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) +#define avail_LVZ(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LVZ)) #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) #define avail_LAM_BH(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM_BH)) @@ -66,6 +67,7 @@ typedef struct DisasContext { TCGv zero; bool la64; /* LoongArch64 mode */ bool va32; /* 32-bit virtual address */ + bool guest_mode; uint32_t cpucfg1; uint32_t cpucfg2; uint32_t cpucfg3; -- 2.52.0
