Allow the breakpoint/watchpoint causing the exception to be passed to the target hook. Unused so far.
Signed-off-by: Richard Henderson <[email protected]> --- include/accel/tcg/cpu-ops.h | 2 +- target/arm/internals.h | 2 +- target/i386/tcg/helper-tcg.h | 2 +- target/ppc/internal.h | 2 +- target/riscv/debug.h | 2 +- target/s390x/tcg/tcg_s390x.h | 2 +- target/xtensa/cpu.h | 2 +- accel/tcg/cpu-exec.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/tcg/system/bpt_helper.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/debug.c | 2 +- target/s390x/tcg/debug.c | 2 +- target/xtensa/helper.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 2dde42cf29..734bcd537b 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -99,7 +99,7 @@ struct TCGCPUOps { /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); /** @debug_excp_handler: Callback for handling debug exceptions */ - void (*debug_excp_handler)(CPUState *cpu); + void (*debug_excp_handler)(CPUState *cpu, CPUBreakpoint *hit); /** @mmu_index: Callback for choosing softmmu mmu index */ int (*mmu_index)(CPUState *cpu, bool ifetch); diff --git a/target/arm/internals.h b/target/arm/internals.h index 9d022245a2..9deb7a6e22 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -700,7 +700,7 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); /* Callback function for when a watchpoint or breakpoint triggers. */ -void arm_debug_excp_handler(CPUState *cs); +void arm_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index f4b2ff740d..01f4a8bcd0 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -42,7 +42,7 @@ bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif -void breakpoint_handler(CPUState *cs); +void breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); /* n must be a constant to be efficient */ static inline target_long lshift(target_long x, int n) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 80f4195378..5d7346a03d 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -303,7 +303,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); -void ppc_cpu_debug_excp_handler(CPUState *cs); +void ppc_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); diff --git a/target/riscv/debug.h b/target/riscv/debug.h index f5234ff763..540835f2d0 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -143,7 +143,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); target_ulong tinfo_csr_read(CPURISCVState *env); -void riscv_cpu_debug_excp_handler(CPUState *cs); +void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); diff --git a/target/s390x/tcg/tcg_s390x.h b/target/s390x/tcg/tcg_s390x.h index 975f60085a..61db0c0b53 100644 --- a/target/s390x/tcg/tcg_s390x.h +++ b/target/s390x/tcg/tcg_s390x.h @@ -26,7 +26,7 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, #ifndef CONFIG_USER_ONLY void s390_cpu_recompute_watchpoints(CPUState *cs); -void s390x_cpu_debug_excp_handler(CPUState *cs); +void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); #endif #endif /* TCG_S390X_H */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c256ab3cc8..663ee23dc4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -621,7 +621,7 @@ void xtensa_translate_init(void); void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); -void xtensa_breakpoint_handler(CPUState *cs); +void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 86ce902c34..3205f365e5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -693,7 +693,7 @@ static inline void cpu_handle_debug_exception(CPUState *cpu) } if (tcg_ops->debug_excp_handler) { - tcg_ops->debug_excp_handler(cpu); + tcg_ops->debug_excp_handler(cpu, cpu->watchpoint_hit); } } diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 293907fdaf..fe8513a5de 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -414,7 +414,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env) } } -void arm_debug_excp_handler(CPUState *cs) +void arm_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { /* * Called by core code when a watchpoint or breakpoint fires; diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/bpt_helper.c index c0c63e3e89..8ba5dfcfc1 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -202,7 +202,7 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) return hit_enabled; } -void breakpoint_handler(CPUState *cs) +void breakpoint_handler(CPUState *cs, CPUBreakpoint *hit) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 12785dc161..51358c901f 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -309,7 +309,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, cpu_loop_exit_restore(cs, retaddr); } -void ppc_cpu_debug_excp_handler(CPUState *cs) +void ppc_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { #if defined(TARGET_PPC64) CPUPPCState *env = cpu_env(cs); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 958c534f4f..a8429778f6 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -914,7 +914,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) BIT(TRIGGER_TYPE_AD_MATCH6); } -void riscv_cpu_debug_excp_handler(CPUState *cs) +void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 9e724bb262..58d9cc6e79 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -49,7 +49,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) } } -void s390x_cpu_debug_excp_handler(CPUState *cs) +void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { CPUS390XState *env = cpu_env(cs); CPUBreakpoint *wp_hit = cs->watchpoint_hit; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 0db5502287..02627ada7c 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -219,7 +219,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) return 0; } -void xtensa_breakpoint_handler(CPUState *cs) +void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit) { CPUXtensaState *env = cpu_env(cs); -- 2.43.0
