These functions are identical. Rename to riscv_cpu_debug_check_bp_wp and install in both target hooks.
Signed-off-by: Richard Henderson <[email protected]> --- target/riscv/debug.h | 3 +-- target/riscv/debug.c | 12 +----------- target/riscv/tcg/tcg-cpu.c | 4 ++-- 3 files changed, 4 insertions(+), 15 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 540835f2d0..fbe6898718 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -144,8 +144,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); target_ulong tinfo_csr_read(CPURISCVState *env); void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); -bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); +bool riscv_cpu_debug_check_bp_wp(CPUState *cs, CPUBreakpoint *bp); void riscv_trigger_realize(CPURISCVState *env); void riscv_trigger_unrealize(CPURISCVState *env); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index f4689519d8..803418f390 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -923,7 +923,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) do_trigger_action(env, DBG_ACTION_BP); } -bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) +bool riscv_cpu_debug_check_bp_wp(CPUState *cs, CPUBreakpoint *bp) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -933,16 +933,6 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) return trigger_common_match(env, trigger_type, i); } -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - int i = wp->id; - trigger_type_t trigger_type = get_trigger_type(env, i); - - return trigger_common_match(env, trigger_type, i); -} - void riscv_trigger_realize(CPURISCVState *env) { int i; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..3701aa6c94 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -292,8 +292,8 @@ const TCGCPUOps riscv_tcg_ops = { .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, .debug_excp_handler = riscv_cpu_debug_excp_handler, - .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, + .debug_check_breakpoint = riscv_cpu_debug_check_bp_wp, + .debug_check_watchpoint = riscv_cpu_debug_check_bp_wp, #endif /* !CONFIG_USER_ONLY */ }; -- 2.43.0
