Introduce a new boolean property, "caps-64bit-addr", to control HCCPARAMS[0] (64-bit Addressing Capability).
When enabled, the EHCI controller advertises support for 64-bit address memory pointers as defined in the EHCI specification (Table 2-7, HCCPARAMS). This allows software to use the 64-bit data structure formats described in Appendix B. When disabled (default), the controller reports 32-bit addressing capability and uses the standard 32-bit data structures. The EHCI CTRLDSSEGMENT register provides the upper 32 bits [63:32] used to form 64-bit addresses for EHCI control data structures. Per EHCI 1.0 spec section 2.3.5, when the HCCPARAMS 64-bit Addressing Capability bit is zero, CTRLDSSEGMENT is not used: software cannot write it and reads must return zero. Add a capability check in the operational register write handler and reject guest writes to CTRLDSSEGMENT when 64-bit addressing is not enabled. Signed-off-by: Jamin Lin <[email protected]> Reviewed-by: Cédric Le Goater <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- hw/usb/hcd-ehci.h | 5 ++++- hw/usb/hcd-ehci.c | 14 +++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index cbc32c296d..f739e6371b 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -261,6 +261,7 @@ struct EHCIState { * Old machine types only transfer 32-bit fetch addresses. */ bool migrate_fetch_addr_64bit; + bool caps_64bit_addr; /* * EHCI spec version 1.0 Section 2.3 @@ -324,7 +325,9 @@ struct EHCIState { #define DEFINE_EHCI_COMMON_PROPERTIES(_state) \ DEFINE_PROP_UINT32("maxframes", _state, ehci.maxframes, 128), \ DEFINE_PROP_BOOL("x-migrate-fetch-addr-64bit", _state, \ - ehci.migrate_fetch_addr_64bit, true) + ehci.migrate_fetch_addr_64bit, true), \ + DEFINE_PROP_BOOL("caps-64bit-addr", _state, \ + ehci.caps_64bit_addr, false) extern const VMStateDescription vmstate_ehci; diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 1a0c580115..e65ea825b0 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1109,6 +1109,15 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, } break; + case CTRLDSSEGMENT: + if (!s->caps_64bit_addr) { + qemu_log_mask(LOG_GUEST_ERROR, + "ehci: write to CTRLDSSEGMENT while " + "64-bit addressing capability is disabled\n"); + return; + } + break; + case ASYNCLISTADDR: if (ehci_async_enabled(s)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -2554,6 +2563,9 @@ void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp) s->maxframes); return; } + if (s->caps_64bit_addr) { + s->caps[0x08] |= BIT(0); + } memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); @@ -2613,7 +2625,7 @@ void usb_ehci_init(EHCIState *s, DeviceState *dev) s->caps[0x05] = 0x00; /* No companion ports at present */ s->caps[0x06] = 0x00; s->caps[0x07] = 0x00; - s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ + s->caps[0x08] = 0x80; /* We can cache whole frame */ s->caps[0x0a] = 0x00; s->caps[0x0b] = 0x00; -- 2.43.0
