Consolidation of different variations of Power ISA 2.07 flags into the PPC2_ISA207 flag has left gaps in the flag encoding. This patch reorders them, restoring the expected incremental order without any gaps, freeing up bits for future use.
Signed-off-by: Chinmay Rath <[email protected]> --- target/ppc/cpu.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4a77607f80..3fb51bbeb8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2578,25 +2578,25 @@ enum { /* ISA 2.06B floating point test instructions */ PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, /* Double precision floating point conversion for signed integer 64 */ - PPC2_FP_CVT_S64 = 0x0000000000010000ULL, + PPC2_FP_CVT_S64 = 0x0000000000001000ULL, /* Transactional Memory (ISA 2.07, Book II) */ - PPC2_TM = 0x0000000000020000ULL, + PPC2_TM = 0x0000000000002000ULL, /* Server PM instructgions (ISA 2.06, Book III) */ - PPC2_PM_ISA206 = 0x0000000000040000ULL, + PPC2_PM_ISA206 = 0x0000000000004000ULL, /* POWER ISA 3.0 */ - PPC2_ISA300 = 0x0000000000080000ULL, + PPC2_ISA300 = 0x0000000000008000ULL, /* POWER ISA 3.1 */ - PPC2_ISA310 = 0x0000000000100000ULL, + PPC2_ISA310 = 0x0000000000010000ULL, /* lwsync instruction */ - PPC2_MEM_LWSYNC = 0x0000000000200000ULL, + PPC2_MEM_LWSYNC = 0x0000000000020000ULL, /* ISA 2.06 BCD assist instructions */ - PPC2_BCDA_ISA206 = 0x0000000000400000ULL, + PPC2_BCDA_ISA206 = 0x0000000000040000ULL, /* PPE42 instructions */ - PPC2_PPE42 = 0x0000000000800000ULL, + PPC2_PPE42 = 0x0000000000080000ULL, /* PPE42X instructions */ - PPC2_PPE42X = 0x0000000001000000ULL, + PPC2_PPE42X = 0x0000000000100000ULL, /* PPE42XM instructions */ - PPC2_PPE42XM = 0x0000000002000000ULL, + PPC2_PPE42XM = 0x0000000000200000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \ -- 2.53.0
