On 26/06/17 04:50AM, Saif Abrar wrote:
> <...snip...>
>
> void pnv_phb4_cfg_core_reset(PCIDevice *d)
> {
> uint8_t *conf = d->config;
> @@ -557,14 +570,56 @@ void pnv_phb4_cfg_core_reset(PCIDevice *d)
> pci_set_long(conf + P16_ECAP, 0x22410026);
> pci_set_long(conf + P32_ECAP, 0x1002A);
> pci_set_long(conf + P32_CAP, 0x103);
> +
> + /* Sticky reset */
> + RC_CONFIG_STICKY_RESET(exp_offset + PCI_EXP_LNKCTL2,
> + PCI_EXP_LNKCTL2_TLS_32_0GT,
> 0xFEFFBF);
This is different for PHB4, which is PCI_EXP_LNKCTL2_TLS_16_0GT (0x4)
and for PHB5, spec says PCI_EXP_LNKCTL2_TLS_32_0GT (0x5)
This doesn't affect skiboot anyways, but good to be correct now.
Rebasing/separating phb5 should fix such nits, let's discuss on it.
Rest looks good to me.
Thanks,
- Aditya G
