On 26/06/17 04:50AM, Saif Abrar wrote: > <...snip...> > > diff --git a/include/hw/pci-host/pnv_phb4_regs.h > b/include/hw/pci-host/pnv_phb4_regs.h > index df5e86d29a..dfd0e01d1e 100644 > --- a/include/hw/pci-host/pnv_phb4_regs.h > +++ b/include/hw/pci-host/pnv_phb4_regs.h > @@ -180,9 +180,11 @@ > #define PHB_M64_AOMASK 0x1d0 > #define PHB_M64_UPPER_BITS 0x1f0 > #define PHB_NXLATE_PREFIX 0x1f8 > -#define PHB_DMARD_SYNC 0x200 > -#define PHB_DMARD_SYNC_START PPC_BIT(0) > -#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) > +#define PHB_DMA_SYNC 0x200 > +#define PHB_DMA_SYNC_RD_START PPC_BIT(0) > +#define PHB_DMA_SYNC_RD_COMPLETE PPC_BIT(1) > +#define PHB_DMA_SYNC_WR_START PPC_BIT(2) > +#define PHB_DMA_SYNC_WR_COMPLETE PPC_BIT(3)
nit: This affects the behaviour in PHB4, where DMARD had bit 2 & 3 as reserved but i don't see it as a concern. Reviewed-by: Aditya Gupta <[email protected]> Thanks, - Aditya G
