Named models provide authoritative ID-register values, so don't derive SVE vector lengths or pauth fields from the host; require explicit SVE lengths and leave the model's pauth fields intact.
Signed-off-by: Khushit Shah <[email protected]> --- target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cdad0fc46d..44dd9acf80 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -38,6 +38,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpu-idregs.h" +#include "arm-cpu-models.h" #include "trace.h" /* convert between <register>_IDX and SYS_<register> */ @@ -134,6 +135,20 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } + /* + * If SVE is enabled but no vector lengths are specified, we must not + * default to the host's supported lengths for named CPU models, as + * this breaks live migration. + */ + { + ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); + if (acc->info && arm_find_model(acc->info->name)) { + error_setg(errp, + "Named CPU models with SVE must set vector lengths"); + return; + } + } + if (kvm_enabled()) { /* Disabling a supported length disables all larger lengths. */ tmp = vq_init & vq_supported; @@ -556,6 +571,20 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) ARMISARegisters *isar = &cpu->isar; uint64_t isar1, isar2; + /* + * For named CPU models the model props write the authoritative + * APA/API/APA3/GPA/GPI/GPA3 values directly into cpu->isar, so do not + * override them here. Since other code relies on cpu->prop_pauth, + * mirror the resulting pauth state into prop_pauth. + */ + { + ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); + if (acc->info && arm_find_model(acc->info->name)) { + cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); + return; + } + } + /* * These properties enable or disable Pauth as a whole, or change * the pauth algorithm, but do not change the set of features that -- 2.52.0
