Signed-off-by: Molly Chen <[email protected]>
---
target/riscv/helper.h | 20 ++++++
target/riscv/insn32.decode | 32 +++++++++
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 20 ++++++
target/riscv/tcg/psimd_helper.c | 78 +++++++++++++++++++++
4 files changed, 150 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 638c7b0629d..9568a7f91c4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1688,3 +1688,23 @@ DEF_HELPER_3(pmulq_w, i64, env, i64, i64)
DEF_HELPER_3(pmulqr_w, i64, env, i64, i64)
DEF_HELPER_3(mulq, i32, env, i32, i32)
DEF_HELPER_3(mulqr, i32, env, i32, i32)
+
+/* Packed SIMD - Q-Format Multiply-Accumulate Operations */
+DEF_HELPER_4(mqacc_h00, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqacc_h01, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqacc_h11, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqracc_h00, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqracc_h01, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqracc_h11, i32, env, i32, i32, i32)
+DEF_HELPER_4(mqacc_w00, i64, env, i64, i64, i64)
+DEF_HELPER_4(mqacc_w01, i64, env, i64, i64, i64)
+DEF_HELPER_4(mqacc_w11, i64, env, i64, i64, i64)
+DEF_HELPER_4(mqracc_w00, i64, env, i64, i64, i64)
+DEF_HELPER_4(mqracc_w01, i64, env, i64, i64, i64)
+DEF_HELPER_4(mqracc_w11, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqacc_w_h00, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqacc_w_h01, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqacc_w_h11, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqracc_w_h00, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqracc_w_h01, i64, env, i64, i64, i64)
+DEF_HELPER_4(pmqracc_w_h11, i64, env, i64, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9c50a4dbf52..e2af5f83965 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1534,3 +1534,35 @@ pmulqr_h 11010 10 ..... ..... 111 ..... 0111011 @r
mulqr 11010 11 ..... ..... 111 ..... 0111011 @r
pmulqr_w 11010 11 ..... ..... 111 ..... 0111011 @r
}
+
+# Packed SIMD - Q-Format Multiply-Accumulate Operations
+{
+ mqacc_h00 11101 00 ..... ..... 111 ..... 0111011 @r
+ pmqacc_w_h00 11101 00 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mqacc_h01 11111 00 ..... ..... 101 ..... 0111011 @r
+ pmqacc_w_h01 11111 00 ..... ..... 101 ..... 0111011 @r
+}
+{
+ mqacc_h11 11111 00 ..... ..... 111 ..... 0111011 @r
+ pmqacc_w_h11 11111 00 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mqracc_h00 11101 10 ..... ..... 111 ..... 0111011 @r
+ pmqracc_w_h00 11101 10 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mqracc_h01 11111 10 ..... ..... 101 ..... 0111011 @r
+ pmqracc_w_h01 11111 10 ..... ..... 101 ..... 0111011 @r
+}
+{
+ mqracc_h11 11111 10 ..... ..... 111 ..... 0111011 @r
+ pmqracc_w_h11 11111 10 ..... ..... 111 ..... 0111011 @r
+}
+mqacc_w00 11101 01 ..... ..... 111 ..... 0111011 @r
+mqacc_w01 11111 01 ..... ..... 101 ..... 0111011 @r
+mqacc_w11 11111 01 ..... ..... 111 ..... 0111011 @r
+mqracc_w00 11101 11 ..... ..... 111 ..... 0111011 @r
+mqracc_w01 11111 11 ..... ..... 101 ..... 0111011 @r
+mqracc_w11 11111 11 ..... ..... 111 ..... 0111011 @r
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index 3535f71de88..cec18255a1e 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -834,3 +834,23 @@ GEN_SIMD_TRANS_64_VXSAT(pmulqr_w)
GEN_SIMD_TRANS_32_VXSAT(mulq)
GEN_SIMD_TRANS_32_VXSAT(mulqr)
+/* Packed SIMD - Q-Format Multiply-Accumulate Operations */
+GEN_SIMD_TRANS_ACC_32(mqacc_h00)
+GEN_SIMD_TRANS_ACC_32(mqacc_h01)
+GEN_SIMD_TRANS_ACC_32(mqacc_h11)
+GEN_SIMD_TRANS_ACC_32(mqracc_h00)
+GEN_SIMD_TRANS_ACC_32(mqracc_h01)
+GEN_SIMD_TRANS_ACC_32(mqracc_h11)
+GEN_SIMD_TRANS_ACC_64(mqacc_w00)
+GEN_SIMD_TRANS_ACC_64(mqacc_w01)
+GEN_SIMD_TRANS_ACC_64(mqacc_w11)
+GEN_SIMD_TRANS_ACC_64(mqracc_w00)
+GEN_SIMD_TRANS_ACC_64(mqracc_w01)
+GEN_SIMD_TRANS_ACC_64(mqracc_w11)
+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h00)
+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h01)
+GEN_SIMD_TRANS_ACC_64(pmqacc_w_h11)
+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h00)
+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h01)
+GEN_SIMD_TRANS_ACC_64(pmqracc_w_h11)
+
diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c
index 11ca17576be..ecdb20bbb58 100644
--- a/target/riscv/tcg/psimd_helper.c
+++ b/target/riscv/tcg/psimd_helper.c
@@ -2655,3 +2655,81 @@ GEN_PSIMD_QMUL(mulq, uint32_t, int32_t, int64_t,
uint32_t,
GEN_PSIMD_QMUL(mulqr, uint32_t, int32_t, int64_t, uint32_t,
EXTRACT32, INSERT32, ELEMS_W, 31, 1LL << 30, INT32_MIN,
INT32_MAX)
+
+
+/* Q-Format Multiply-Accumulate Operations */
+
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_h00, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 0, 0, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_h01, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 0, 1, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_h11, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 1, 1, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_h00, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 0, 0, 15,
+ 1LL << 14, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_h01, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 0, 1, 15,
+ 1LL << 14, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_h11, uint32_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 0, 1, 1, 15,
+ 1LL << 14, PSIMD_MUL_S64)
+
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_w00, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 0, 0, 31, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_w01, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 0, 1, 31, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqacc_w11, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 1, 1, 31, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_w00, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 0, 0, 31,
+ 1LL << 30, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_w01, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 0, 1, 31,
+ 1LL << 30, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(mqracc_w11, uint64_t, int32_t, int32_t,
+ int64_t, int64_t, int64_t, uint64_t, EXTRACT32,
+ EXTRACT64, INSERT64, ELEMS_D, 0, 1, 1, 31,
+ 1LL << 30, PSIMD_MUL_S64)
+
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqacc_w_h00, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 0, 0, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqacc_w_h01, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 0, 1, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqacc_w_h11, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 1, 1, 15, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqracc_w_h00, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 0, 0, 15,
+ 1LL << 14, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqracc_w_h01, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 0, 1, 15,
+ 1LL << 14, PSIMD_MUL_S64)
+GEN_PSIMD_QMUL_ACC_INDEXED(pmqracc_w_h11, uint64_t, int16_t, int16_t,
+ int32_t, int64_t, int32_t, uint32_t, EXTRACT16,
+ EXTRACT32, INSERT32, ELEMS_W, 2, 1, 1, 15,
+ 1LL << 14, PSIMD_MUL_S64)
--
2.34.1
