Signed-off-by: Molly Chen <[email protected]>
---
target/riscv/helper.h | 14 +++++++
target/riscv/insn32.decode | 14 +++++++
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 14 +++++++
target/riscv/tcg/psimd_helper.c | 41 +++++++++++++++++++++
4 files changed, 83 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b0743d19177..fb95a9f71b5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1742,3 +1742,17 @@ DEF_HELPER_4(pm2addau_w, i64, env, i64, i64, i64)
DEF_HELPER_4(pm2adda_wx, i64, env, i64, i64, i64)
DEF_HELPER_4(pm2suba_w, i64, env, i64, i64, i64)
DEF_HELPER_4(pm2suba_wx, i64, env, i64, i64, i64)
+
+/* Packed SIMD - Four-Way Multiply and Accumulate Operations */
+DEF_HELPER_3(pm4add_b, tl, env, tl, tl)
+DEF_HELPER_3(pm4addsu_b, tl, env, tl, tl)
+DEF_HELPER_3(pm4addu_b, tl, env, tl, tl)
+DEF_HELPER_4(pm4adda_b, tl, env, tl, tl, tl)
+DEF_HELPER_4(pm4addasu_b, tl, env, tl, tl, tl)
+DEF_HELPER_4(pm4addau_b, tl, env, tl, tl, tl)
+DEF_HELPER_3(pm4add_h, i64, env, i64, i64)
+DEF_HELPER_3(pm4addsu_h, i64, env, i64, i64)
+DEF_HELPER_3(pm4addu_h, i64, env, i64, i64)
+DEF_HELPER_4(pm4adda_h, i64, env, i64, i64, i64)
+DEF_HELPER_4(pm4addasu_h, i64, env, i64, i64, i64)
+DEF_HELPER_4(pm4addau_h, i64, env, i64, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1c8bdde25c2..8720fedb592 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1600,3 +1600,17 @@ pm2addau_w 10101 01 ..... ..... 101 ..... 0111011 @r
pm2adda_wx 10011 01 ..... ..... 101 ..... 0111011 @r
pm2suba_w 11001 01 ..... ..... 101 ..... 0111011 @r
pm2suba_wx 11011 01 ..... ..... 101 ..... 0111011 @r
+
+# Packed SIMD - Four-Way Multiply and Accumulate Operations
+pm4add_b 10000 10 ..... ..... 101 ..... 0111011 @r
+pm4addsu_b 11100 10 ..... ..... 101 ..... 0111011 @r
+pm4addu_b 10100 10 ..... ..... 101 ..... 0111011 @r
+pm4adda_b 10001 10 ..... ..... 101 ..... 0111011 @r
+pm4addasu_b 11101 10 ..... ..... 101 ..... 0111011 @r
+pm4addau_b 10101 10 ..... ..... 101 ..... 0111011 @r
+pm4add_h 10000 11 ..... ..... 101 ..... 0111011 @r
+pm4addsu_h 11100 11 ..... ..... 101 ..... 0111011 @r
+pm4addu_h 10100 11 ..... ..... 101 ..... 0111011 @r
+pm4adda_h 10001 11 ..... ..... 101 ..... 0111011 @r
+pm4addasu_h 11101 11 ..... ..... 101 ..... 0111011 @r
+pm4addau_h 10101 11 ..... ..... 101 ..... 0111011 @r
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index cf670b144c3..6c344a66dc8 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -888,3 +888,17 @@ GEN_SIMD_TRANS_ACC_64(pm2adda_wx)
GEN_SIMD_TRANS_ACC_64(pm2suba_w)
GEN_SIMD_TRANS_ACC_64(pm2suba_wx)
+/* Packed SIMD - Four-Way Multiply and Accumulate Operations */
+GEN_SIMD_TRANS(pm4add_b)
+GEN_SIMD_TRANS(pm4addsu_b)
+GEN_SIMD_TRANS(pm4addu_b)
+GEN_SIMD_TRANS_ACC(pm4adda_b)
+GEN_SIMD_TRANS_ACC(pm4addasu_b)
+GEN_SIMD_TRANS_ACC(pm4addau_b)
+GEN_SIMD_TRANS_64(pm4add_h)
+GEN_SIMD_TRANS_64(pm4addsu_h)
+GEN_SIMD_TRANS_64(pm4addu_h)
+GEN_SIMD_TRANS_ACC_64(pm4adda_h)
+GEN_SIMD_TRANS_ACC_64(pm4addasu_h)
+GEN_SIMD_TRANS_ACC_64(pm4addau_h)
+
diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c
index bad04937b54..e7c7e554938 100644
--- a/target/riscv/tcg/psimd_helper.c
+++ b/target/riscv/tcg/psimd_helper.c
@@ -2849,3 +2849,44 @@ GEN_PSIMD_2WAY_MUL_ACC(pm2suba_wx, uint64_t, int32_t,
int32_t,
int64_t, int64_t, uint64_t, EXTRACT32, EXTRACT64,
INSERT64, ELEMS_D, 0, 0, 1, 1, 0, PSIMD_MUL_S64,
PSIMD_COMB_SUB)
+
+
+/* Four-Way Multiply and Accumulate Operations */
+
+GEN_PSIMD_4WAY_MUL(pm4add_b, target_ulong, int8_t, int8_t,
+ int32_t, uint32_t, EXTRACT8, INSERT32, ELEMS_W, 4,
+ PSIMD_MUL_S32)
+GEN_PSIMD_4WAY_MUL(pm4addsu_b, target_ulong, int8_t, uint8_t,
+ int32_t, uint32_t, EXTRACT8, INSERT32, ELEMS_W, 4,
+ PSIMD_MUL_SU32)
+GEN_PSIMD_4WAY_MUL(pm4addu_b, target_ulong, uint8_t, uint8_t,
+ uint32_t, uint32_t, EXTRACT8, INSERT32, ELEMS_W, 4,
+ PSIMD_MUL_U32)
+GEN_PSIMD_4WAY_MUL_ACC(pm4adda_b, target_ulong, int8_t, int8_t,
+ int32_t, int32_t, uint32_t, EXTRACT8, EXTRACT32,
+ INSERT32, ELEMS_W, 4, PSIMD_MUL_S32)
+GEN_PSIMD_4WAY_MUL_ACC(pm4addasu_b, target_ulong, int8_t, uint8_t,
+ int32_t, int32_t, uint32_t, EXTRACT8, EXTRACT32,
+ INSERT32, ELEMS_W, 4, PSIMD_MUL_SU32)
+GEN_PSIMD_4WAY_MUL_ACC(pm4addau_b, target_ulong, uint8_t, uint8_t,
+ uint32_t, uint32_t, uint32_t, EXTRACT8, EXTRACT32,
+ INSERT32, ELEMS_W, 4, PSIMD_MUL_U32)
+
+GEN_PSIMD_4WAY_MUL(pm4add_h, uint64_t, int16_t, int16_t,
+ int64_t, uint64_t, EXTRACT16, INSERT64, ELEMS_D, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_4WAY_MUL(pm4addsu_h, uint64_t, int16_t, uint16_t,
+ int64_t, uint64_t, EXTRACT16, INSERT64, ELEMS_D, 0,
+ PSIMD_MUL_SU64)
+GEN_PSIMD_4WAY_MUL(pm4addu_h, uint64_t, uint16_t, uint16_t,
+ uint64_t, uint64_t, EXTRACT16, INSERT64, ELEMS_D, 0,
+ PSIMD_MUL_U64)
+GEN_PSIMD_4WAY_MUL_ACC(pm4adda_h, uint64_t, int16_t, int16_t,
+ int64_t, int64_t, uint64_t, EXTRACT16, EXTRACT64,
+ INSERT64, ELEMS_D, 0, PSIMD_MUL_S64)
+GEN_PSIMD_4WAY_MUL_ACC(pm4addasu_h, uint64_t, int16_t, uint16_t,
+ int64_t, int64_t, uint64_t, EXTRACT16, EXTRACT64,
+ INSERT64, ELEMS_D, 0, PSIMD_MUL_SU64)
+GEN_PSIMD_4WAY_MUL_ACC(pm4addau_h, uint64_t, uint16_t, uint16_t,
+ uint64_t, uint64_t, uint64_t, EXTRACT16, EXTRACT64,
+ INSERT64, ELEMS_D, 0, PSIMD_MUL_U64)
--
2.34.1
