Hi Khushit, On 7/16/26 11:38 PM, Khushit Shah wrote: > Signed-off-by: Khushit Shah <[email protected]> > --- > target/arm/cpu-sysregs.h.inc | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 05f558610b..2188cd7be0 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -19,6 +19,7 @@ DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) > DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) > DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) > DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) > +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) Please could you send a branch. It is difficult to understand on which code base you applied thise series as ID_AA64ISAR3_EL1 definition is already upstream
Thanks Eric > DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) > DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) > DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
