This patchset adds SiFive's custom int8 matrix-multiply vector
extensions Xsfvqmaccdod and Xsfvqmaccqoq. Each extension provides 4
signedness variants (unsigned/unsigned, signed/signed,
unsigned/signed, signed/unsigned) for a total of 8 instructions:
sf.vqmacc{u,,us,su}.{4x8x4,2x8x2}.The toolchains support Xsfvqmaccdod/Xsfvqmaccqoq extensions: - LLVM 18.1.0 - llvm/llvm-project#68295, commit d1985e3d1fed, merged 2023-10-20. https://github.com/llvm/llvm-project/pull/68295 - GCC 15 - commit 139bd3198a73 ("RISC-V: Add the mini support for SiFive extensions"), 2024-11-17. References: - SiFive Int8 Matrix Multiplication Extensions Specification https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification Frank Chang (2): target/riscv: Add SiFive custom int8 matmul extension implied rules target/riscv: rvv: Add SiFive custom int8 matmul instructions Jason Chien (1): disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq Max Chou (2): target/riscv: Add cfg property for SiFive int8 matmul extensions tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions MAINTAINERS | 9 + disas/meson.build | 3 +- disas/riscv-xsf.c | 79 ++++++ disas/riscv-xsf.h | 18 ++ disas/riscv.c | 2 + disas/riscv.h | 1 + target/riscv/cpu.c | 21 ++ target/riscv/cpu_cfg.h | 5 + target/riscv/cpu_cfg_fields.h.inc | 2 + target/riscv/helper.h | 10 + target/riscv/meson.build | 1 + target/riscv/tcg/insn_trans/trans_xsf.c.inc | 98 ++++++++ target/riscv/tcg/tcg-cpu.c | 16 ++ target/riscv/tcg/translate.c | 3 + target/riscv/tcg/vector_helper.c | 74 ++++++ target/riscv/xsf.decode | 30 +++ tests/tcg/riscv64/Makefile.softmmu-target | 7 + tests/tcg/riscv64/test-xsfvqmacc.S | 260 ++++++++++++++++++++ 18 files changed, 638 insertions(+), 1 deletion(-) create mode 100644 disas/riscv-xsf.c create mode 100644 disas/riscv-xsf.h create mode 100644 target/riscv/tcg/insn_trans/trans_xsf.c.inc create mode 100644 target/riscv/xsf.decode create mode 100644 tests/tcg/riscv64/test-xsfvqmacc.S -- 2.55.0
