From: Jason Chien <[email protected]> Add disassembler support for all SiFive custom int8 matrix-multiply instructions: sf.vqmacc{u,,us,su}.4x8x4 and sf.vqmacc{u,,us,su}.2x8x2.
These instructions share opcode 0b1011011 and funct3 0b010, and are distinguished by funct6: 60-63 for the 4x8x4 (Xsfvqmaccqoq) tile and 44-47 for the 2x8x2 (Xsfvqmaccdod) tile. Signed-off-by: Jason Chien <[email protected]> Signed-off-by: Max Chou <[email protected]> --- MAINTAINERS | 1 + disas/meson.build | 3 +- disas/riscv-xsf.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++ disas/riscv-xsf.h | 18 +++++++++++ disas/riscv.c | 2 ++ disas/riscv.h | 1 + 6 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 disas/riscv-xsf.c create mode 100644 disas/riscv-xsf.h diff --git a/MAINTAINERS b/MAINTAINERS index 94cd63eeba..1a40d86685 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -395,6 +395,7 @@ L: [email protected] S: Supported F: target/riscv/xsf.decode F: target/riscv/tcg/insn_trans/trans_xsf.c.inc +F: disas/riscv-xsf* RENESAS RX CPUs R: Yoshinori Sato <[email protected]> diff --git a/disas/meson.build b/disas/meson.build index 42977a1f74..9135716268 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -8,7 +8,8 @@ common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', 'riscv-xventana.c', - 'riscv-xlrbr.c' + 'riscv-xlrbr.c', + 'riscv-xsf.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) diff --git a/disas/riscv-xsf.c b/disas/riscv-xsf.c new file mode 100644 index 0000000000..8f752657a7 --- /dev/null +++ b/disas/riscv-xsf.c @@ -0,0 +1,79 @@ +/* + * QEMU RISC-V Disassembler for xsf (SiFive vendor extensions). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "disas/riscv.h" +#include "disas/riscv-xsf.h" + +typedef enum { + /* 0 is reserved for rv_op_illegal. */ + xsf_op_sf_vqmaccu_4x8x4 = 1, + xsf_op_sf_vqmacc_4x8x4 = 2, + xsf_op_sf_vqmaccus_4x8x4 = 3, + xsf_op_sf_vqmaccsu_4x8x4 = 4, + xsf_op_sf_vqmaccu_2x8x2 = 5, + xsf_op_sf_vqmacc_2x8x2 = 6, + xsf_op_sf_vqmaccus_2x8x2 = 7, + xsf_op_sf_vqmaccsu_2x8x2 = 8, +} rv_xsf_op; + +const rv_opcode_data xsf_opcode_data[] = { + { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, + { "sf.vqmaccu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmacc.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmaccus.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmaccsu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmaccu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmacc.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmaccus.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, + { "sf.vqmaccsu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2, NULL, 0, 0, 0 }, +}; + +void decode_xsf(rv_decode *dec, rv_isa isa) +{ + rv_inst inst = dec->inst; + rv_opcode op = rv_op_illegal; + + switch ((inst >> 0) & 0b1111111) { + case 0b1011011: + switch ((inst >> 12) & 0b111) { + case 0b010: + switch ((inst >> 26) & 0b111111) { + case 60: + op = xsf_op_sf_vqmaccu_4x8x4; + break; + case 61: + op = xsf_op_sf_vqmacc_4x8x4; + break; + case 62: + op = xsf_op_sf_vqmaccus_4x8x4; + break; + case 63: + op = xsf_op_sf_vqmaccsu_4x8x4; + break; + case 44: + op = xsf_op_sf_vqmaccu_2x8x2; + break; + case 45: + op = xsf_op_sf_vqmacc_2x8x2; + break; + case 46: + op = xsf_op_sf_vqmaccus_2x8x2; + break; + case 47: + op = xsf_op_sf_vqmaccsu_2x8x2; + break; + } + break; + } + break; + } + + dec->op = op; +} diff --git a/disas/riscv-xsf.h b/disas/riscv-xsf.h new file mode 100644 index 0000000000..b8462c356e --- /dev/null +++ b/disas/riscv-xsf.h @@ -0,0 +1,18 @@ +/* + * QEMU disassembler -- RISC-V specific header (xsf*). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_XSF_H +#define DISAS_RISCV_XSF_H + +#include "disas/riscv.h" + +extern const rv_opcode_data xsf_opcode_data[]; + +void decode_xsf(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_XSF_H */ diff --git a/disas/riscv.c b/disas/riscv.c index 7f1b262773..032cd31e35 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -27,6 +27,7 @@ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" #include "disas/riscv-xlrbr.h" +#include "disas/riscv-xsf.h" typedef enum { /* 0 is reserved for rv_op_illegal. */ @@ -5454,6 +5455,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr }, + { has_xsf_p, xsf_opcode_data, decode_xsf }, }; for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { diff --git a/disas/riscv.h b/disas/riscv.h index 379e642ec8..66683201b9 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -280,6 +280,7 @@ enum { #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" #define rv_fmt_vd_vs2_uimm "O\tD,F,u" #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" +#define rv_fmt_vd_vs1_vs2 "O\tD,E,F" #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" -- 2.55.0
