On Tue, 21 Jul 2026 at 20:03, Michael Tokarev <[email protected]> wrote: > > On 7/13/26 09:46, Jay Chang wrote: > > The Marvell 88E1111 PHY register 17 (PHY Specific Status Register) > > bit 10 reports real-time link status. Previously, this register > > returned a fixed value of 0x8800 with bit 10 always cleared, > > causing U-Boot to always detect "No link" even when the link > > was up. > > > > Signed-off-by: Jay Chang <[email protected]> > > Reviewed-by: Frank Chang <[email protected]> > > I'm picking this up for qemu-stable. > Please let me know if I should not. > > > --- > > hw/net/xilinx_axienet.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c > > index 970732b162..9f5f65ecfa 100644 > > --- a/hw/net/xilinx_axienet.c > > +++ b/hw/net/xilinx_axienet.c > > @@ -103,6 +103,9 @@ static unsigned int tdk_read(struct PHY *phy, unsigned > > int req) > > case 17: > > /* Marvell PHY on many xilinx boards. */ > > r = 0x8000; /* 1000Mb */ > > + if (phy->link) { > > + r |= 0x0400; /* Link is up */ > > + } > > Shouldn't we clear this bit somewhere?
You mean phy->link ? Probably that should be controlled by the network backend. But that's a pre-existing thing (we already report phy->link in a different PHY register). -- PMM
