Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/helper.c | 18 ++++++++++++++++--
target/arm/tcg/op_helper.c | 4 +++-
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 971f0fbc08..022a63a511 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5894,8 +5894,22 @@ static CPAccessResult access_v7a_tid3(CPUARMState *env,
const ARMCPRegInfo *ri,
* Any other registers in the TID3 trap space should use access_tid3(),
* so that they trap on v8 and above, but not on v7.
*/
- if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
- return CP_ACCESS_TRAP_EL2;
+ switch (arm_current_el(env)) {
+ case 1:
+ if (arm_hcr_el2_eff(env) & HCR_TID3) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ /* fall through */
+ case 2:
+ /* Note FEAT_IDTE3 does not trap AArch32 sysregs. */
+ if (ri->state == ARM_CP_STATE_AA64 && (env->cp15.scr_el3 & SCR_TID3)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ break;
+ case 3:
+ break;
+ default:
+ g_assert_not_reached();
}
return CP_ACCESS_OK;
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 93336daf53..9b651104a7 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -1197,7 +1197,9 @@ void HELPER(tid3_udef_el1)(CPUARMState *env, uint32_t
syndrome)
target_el = 2;
excp = EXCP_HYP_TRAP;
} else if (is_a64(env)) {
- if (!cpu_isar_feature(aa64_idst, env_archcpu(env))) {
+ if (env->cp15.scr_el3 & SCR_TID3) {
+ target_el = 3;
+ } else if (!cpu_isar_feature(aa64_idst, env_archcpu(env))) {
syndrome = syn_uncategorized();
}
} else {
--
2.43.0
