>From a13bfa64b84ac70c9e257253616ce650fc3e794b Mon Sep 17 00:00:00 2001 From: Flavien Solt <[email protected]> Date: Mon, 27 Jul 2026 09:45:06 +0800 Subject: [PATCH v3 0/3] riscv-iommu: always send MRIF notice MSI
The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF even when the destination interrupt is disabled. QEMU currently reads the MRIF interrupt-enable word and returns without sending the notice when the matching bit is clear. Patch 1 lets iommu-testdev select an MSI payload and supplies its PCI requester ID. Patch 2 removes the invalid enable-bit gate. Patch 3 checks both enable states through qemu-system-riscv64. The complete RISC-V IOMMU qtest suite passes: MRIF notice: enable=0 pending=0x20 notice=0x12d MRIF notice: enable=1 pending=0x20 notice=0x12d 6/6 tests passed This revision resends unchanged code after hunk headers in v2 were hard-wrapped in transit. The messages use patch-safe MIME transfer encoding. Patch 1 now carries Tao Tang's Reviewed-by tag. Changes in v3: - Resend with patch-safe MIME transfer encoding. - Add Tao Tang's Reviewed-by tag to patch 1. Changes in v2: - Wrap the fix commit message. - Keep the existing notification comment. - Add deterministic IE-clear and IE-set qtests. Flavien Solt (3): hw/misc/iommu-testdev: support PCI MSI test writes hw/riscv/riscv-iommu.c: always send MRIF notice MSI tests/qtest: add RISC-V IOMMU MRIF notice tests hw/misc/iommu-testdev.c | 14 ++++- hw/riscv/riscv-iommu.c | 13 ---- include/hw/misc/iommu-testdev.h | 1 + tests/qtest/iommu-riscv-test.c | 102 ++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+), 15 deletions(-) base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05 -- 2.54.0
