The AIA specification requires an IOMMU to send the configured notice
MSI after storing an MSI to an MRIF, even when the corresponding
interrupt-enable bit is clear.
riscv_iommu_msi_write() currently reads the MRIF interrupt-enable
doubleword and suppresses the notice MSI when the matching bit is zero.
This makes notice delivery depend on a bit that AIA requires the IOMMU
to ignore.
Remove the enable-word read and send the notice MSI unconditionally
after updating the MRIF pending bit.
Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Cc: [email protected]
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Flavien Solt <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
Tested-by: Chao Liu <[email protected]>
---
hw/riscv/riscv-iommu.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f6865d1..2bbac30 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -788,19 +788,6 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState
*s,
goto err;
}
- /* Get MRIF enable bits */
- addr = addr + sizeof(intn);
- res = dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs);
- if (res != MEMTX_OK) {
- cause = RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;
- goto err;
- }
-
- if (!(intn & data)) {
- /* notification disabled, MRIF update completed. */
- return MEMTX_OK;
- }
-
/* Send notification message */
addr = PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN));
n190 = get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |
--
2.54.0
