The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF even when the destination interrupt is disabled. QEMU currently reads the MRIF interrupt-enable word and returns without sending the notice when the matching bit is clear.
Patch 1 lets iommu-testdev select an MSI payload and supplies its PCI requester ID. Patch 2 removes the invalid enable-bit gate. Patch 3 checks both enable states through qemu-system-riscv64. The complete RISC-V IOMMU qtest suite passes: MRIF notice: enable=0 pending=0x20 notice=0x12d MRIF notice: enable=1 pending=0x20 notice=0x12d 6/6 tests passed V3 used MIME transfer encoding to protect the patch body, but lore still received five hard-wrapped hunk headers. This revision resends unchanged code through b4 and carries the review tags received on v1 and v3. Changes in v4: - Resend through b4 after the v3 lore copy remained line-wrapped. - Restore Daniel Henrique Barboza's Reviewed-by tag on patch 2. - Add review and test tags from Nutty Liu and Chao Liu. Changes in v3: - Attempt to protect the patch body with MIME transfer encoding. - Add Tao Tang's Reviewed-by tag to patch 1. Changes in v2: - Wrap the fix commit message. - Keep the existing notification comment. - Add deterministic IE-clear and IE-set qtests. Signed-off-by: Flavien Solt <[email protected]> --- Flavien Solt (3): hw/misc/iommu-testdev: support PCI MSI test writes hw/riscv/riscv-iommu.c: always send MRIF notice MSI tests/qtest: add RISC-V IOMMU MRIF notice tests hw/misc/iommu-testdev.c | 14 +++++- hw/riscv/riscv-iommu.c | 13 ----- include/hw/misc/iommu-testdev.h | 1 + tests/qtest/iommu-riscv-test.c | 102 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+), 15 deletions(-) --- base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05 change-id: 20260727-qemu-mrif-v4-c8e3c3a48b9c Best regards, -- Flavien Solt <[email protected]>
